Transfer Replicator for Automotive Memory Fault Tolerance
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Solution Overview
Problem
Current solutions for protecting memory systems in automotive control systems from faults are costly and complex, with existing fault-tolerant methods providing limited fault coverage and increased software integration complexity.
Innovation Solution
A system-on-chip with a transfer replicator hardware circuit block that replicates CPU-to-memory access requests multiple times and checks for data identity, facilitating fault tolerance through majority voting and reducing the need for expensive error-correcting code mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant systems or sub-systems are provided to protect memory and interface from faults, then fault tolerance is improved, but hardware cost and system complexity increase significantly
Solution Approach 1:
The patent divides the fault protection function into separate segments: the transfer replicator handles request replication and data comparison, while the memory subsystem handles data storage. This segmentation allows each component to be optimized independently and reduces overall system complexity compared to full redundancy.
Solution Approach 2:
The patent creates copies of memory access requests through the transfer replicator, which replicates requests multiple times and compares the resulting data. This copying mechanism provides fault detection and correction without requiring complete redundant systems, thereby reducing hardware cost and complexity while maintaining reliability.
2Reliability
If multiple replicas of memory blocks are provided, then fault coverage is improved, but software integration complexity increases hugely
Solution Approach 1:
The transfer replicator automatically performs request replication, data retrieval, and result comparison without software intervention. This self-service mechanism eliminates the need for complex software redundancy management, allowing the system to achieve high fault coverage while keeping software integration simple.
Solution Approach 2:
The transfer replicator acts as an intermediary between the CPU and memory blocks, handling all fault protection operations. This intermediary absorbs the complexity of redundant operations, presenting a simple interface to both the CPU and memory subsystems, thereby reducing software integration complexity while maintaining high fault coverage.
3Reliability
If ECC memory blocks with EDC technique are employed, then some fault coverage is provided, but the coverage is limited to single- or two-bit faults
Solution Approach 1:
The transfer replicator dynamically adjusts its operation based on the number of replicas created and the comparison results. This dynamic approach allows the system to detect and correct a broader range of faults including multi-bit faults and common cause faults, exceeding the limited coverage of static ECC/EDC techniques.
Solution Approach 2:
The patent changes the fundamental parameter of fault detection from bit-level correction (ECC) to request-level replication and data comparison. By changing this parameter, the system achieves broader fault coverage including single-point faults, common cause faults, and multi-bit faults, while maintaining hardware efficiency.
4Reliability
If full system redundancy is implemented, then fault tolerance is maximized, but hardware cost becomes huge
Solution Approach 1:
The patent applies partial redundancy by replicating only the memory access requests and comparing data results, rather than replicating entire systems. This partial action approach provides sufficient fault tolerance for critical memory operations while significantly reducing hardware cost compared to full system redundancy.
Solution Approach 2:
The transfer replicator creates copies of memory access requests and compares the resulting data to detect faults. This copying mechanism provides effective fault protection at low cost by replicating only the necessary control signals and data paths, avoiding the huge hardware cost of full system redundancy while maintaining high fault tolerance.
Data Source
AI summary
A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.