Transfer Sequencer Reduces Processor Load in Storage Systems
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Solution Overview
Problem
Current storage systems face a significant load on processors due to the lack of efficient control over multiple data transfers between memories, leading to increased processing overhead and inefficiency.
Innovation Solution
The introduction of a transfer sequencer that requests data transfers from multiple transfer controllers, reducing the processor's load by managing data transfers between memories and eliminating the need for direct processor intervention in each transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the processor directly controls each data transfer between memories, then data transfer control is achieved, but the processor load increases significantly
Solution Approach 1:
A transfer sequencer is introduced as an intermediary component between the processor and multiple DMA controllers. The transfer sequencer receives transfer requests from the processor, manages the scheduling and coordination of multiple DMA controllers, and handles transfer completion notifications. This intermediary absorbs the complexity of controlling multiple concurrent transfers, allowing the processor to simply issue high-level transfer requests without being burdened by the complexity of coordinating multiple DMA controllers directly.
2Reliability
If the processor handles each transfer completion notification, then transfer status is tracked, but processing overhead increases due to frequent process switching
Solution Approach 1:
The transfer sequencer acts as an intermediary that receives transfer completion notifications from DMA controllers and manages the tracking of transfer status. Instead of the processor being directly notified and performing process switches for each completion, the transfer sequencer consolidates this functionality. It maintains information about ongoing transfers, processes completions, and only notifies the processor when necessary, thereby eliminating frequent process switches while maintaining reliable transfer status tracking.
3Productivity
If multiple DMA controllers operate independently, then data transfer capability is increased, but coordination complexity increases
Solution Approach 1:
The transfer sequencer serves as a central coordinator that manages multiple DMA controllers. It receives transfer requests from the processor, distributes appropriate requests to relevant DMA controllers, and coordinates their operations to ensure proper data flow between memories. This centralized coordination through the transfer sequencer allows multiple DMA controllers to operate in parallel with high data transfer capability while the sequencer handles the complexity of coordination, arbitration, and conflict resolution.
Solution Approach 2:
The system segments the data transfer functionality by separating the control plane (transfer sequencer) from the execution plane (multiple DMA controllers). The transfer sequencer handles high-level transfer management, while individual DMA controllers handle specific transfer operations. This segmentation allows each component to be optimized for its specific function while reducing the coordination burden on the processor.
Data Source
AI summary
It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.