Transfer Transistor Sharing for 3D Memory Integration
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Solution Overview
Problem
Conventional stacked non-volatile semiconductor memory devices face increased complexity and area requirements due to the number of transfer transistors and peripheral circuitry, which hinders memory integration and efficiency.
Innovation Solution
The design incorporates a control circuit that utilizes transfer transistors to selectively connect and disconnect voltage supply lines, reducing the number of transfer transistors needed by sharing them between dummy and select gate lines, thereby minimizing the circuit area while maintaining operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stacked non-volatile semiconductor memory devices are designed with three-dimensionally arranged memory cells, then memory integration is improved, but the number of transfer transistors increases and peripheral circuit area increases
Solution Approach 1:
The transfer transistor is designed to perform multiple functions: it controls voltage supply to both the select gate line and the dummy gate line, and also functions as a block selection transistor. This multi-functionality reduces the total number of transfer transistors needed in the peripheral circuits while maintaining the three-dimensional memory cell structure
Solution Approach 2:
The patent combines the voltage control function for the select gate line and dummy gate line into a single transfer transistor. By merging these control functions and sharing the transfer transistor between multiple lines, the peripheral circuit area is reduced while preserving memory integration benefits
2Productivity
If conventional stacked non-volatile semiconductor memory devices are designed with three-dimensionally arranged memory cells, then memory integration is improved, but peripheral circuit area increases
Solution Approach 1:
The transfer transistor serves multiple purposes including voltage supply control and block selection, reducing the need for separate dedicated transistors for each function and thereby minimizing peripheral circuit footprint
Solution Approach 2:
The patent applies different voltage levels selectively to different regions (selected vs. non-selected blocks) through the transfer transistor's switching action, enabling local control that reduces overall circuit complexity and area
Data Source
AI summary
Plural memory-strings are arranged in each memory-blocks, the memory-strings extending perpendicular to a substrate. Each memory-string includes plural memory-transistors and dummy-transistors connected in series. The drain-side select gate line and source-side select gate line are supplied with a voltage from the control circuit through the transfer-transistors when corresponding one of the memory blocks is selected. The drain-side select gate line and source-side select gate line are set in a floating state by the transfer-transistors that are rendered non-conductive when corresponding one of the memory-blocks is not selected. The dummy word-line is supplied with a voltage from the control circuit through a first transfer-transistor that are rendered conductive when corresponding memory block is selected. The dummy word-line is supplied with a voltage through a second transfer transistor different from the first transfer-transistor when corresponding memory-block is not selected.