Transfer Wafer Bonding III-V Chips Silicon Wafers
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Solution Overview
Problem
The integration of III-V semiconductor chips with silicon wafers for optical devices is challenging due to lattice mismatch and the limitations of existing bonding techniques, which face issues with thermal expansion coefficient mismatch and the compatibility of compliant resins with high annealing temperatures.
Innovation Solution
A method involving a transfer wafer with a silicon substrate and a compliant material that can withstand high temperatures, using ion implantation to separate the transfer substrate during bonding, ensuring matched thermal expansion coefficients and stable chip alignment, and employing a compliant resin to secure chips with pits for uniform pressure and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transparent materials (glass or sapphire) are used as transfer substrate to allow UV laser de-bonding of resin, then resin removal is enabled, but thermal expansion mismatch causes chip misalignment during annealing
Solution Approach 1:
The patent introduces an intermediary layer (silicon oxide or silicon nitride) between the transparent transfer substrate and the chips. This intermediary layer has a thermal expansion coefficient matched to silicon, compensating for the thermal expansion mismatch of the transparent substrate. During annealing, this layer prevents chip misalignment while allowing UV laser transmission for resin de-bonding.
Solution Approach 2:
The patent changes the thermal expansion parameter by using a multi-layer substrate structure where the intermediary layer's thermal expansion properties compensate for the transparent substrate's mismatch. This parameter matching enables both UV transparency and thermal stability during the bonding process.
2Reliability
If high annealing temperatures are used for effective chip bonding, then bonding reliability is improved, but compliant resin cannot withstand the temperature
Solution Approach 1:
The patent uses the transfer substrate with matched thermal expansion as an intermediary that protects the resin from direct thermal stress. The substrate's thermal properties are engineered to be compatible with high-temperature annealing, allowing the resin to maintain its bonding function while the substrate absorbs thermal expansion stresses.
Solution Approach 2:
The patent changes the thermal parameters of the transfer substrate by selecting materials with thermal expansion coefficients matched to silicon. This enables the substrate to withstand high annealing temperatures without causing misalignment, thereby allowing effective thermal bonding while protecting the resin.
3Area of stationary object
If large-diameter non-silicon substrates are used for transfer, then chip placement area is increased, but thermal expansion difference exceeds chip placement tolerance
Solution Approach 1:
The patent segments the transfer substrate into a multi-layer structure with an intermediary layer that has matched thermal expansion properties. This segmentation allows the large-diameter substrate to maintain dimensional stability during thermal cycling, keeping chip placement within tolerance while providing adequate placement area.
Solution Approach 2:
The patent uses composite material structure combining transparent substrate with intermediary layer. This composite approach leverages the UV transparency of the first layer and the thermal expansion matching of the second layer, enabling both large area placement and precision alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables reliable bonding of III-V semiconductor chips to silicon wafers with minimal misalignment and efficient removal of the transfer substrate, facilitating the integration of advanced optical devices while accommodating varying chip thicknesses and high annealing temperatures.
Implementation Method 1
Removing the transfer substrate (i.e., de-bonding) is achieved with the use of ion implantation (e.g., using hydrogen, He, B, and/or Si ions) in the transfer substrate followed by heat treatment
Implementation Method 2
both the transfer substrate and the target substrate have matched thermal expansion coefficient (e.g., both silicon), the relative position of the chips between the transfer substrate and the target substrate do not change much, if any, during annealing
Data Source
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AI summary
A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.