Transflective LCD Panel Gate Line Shielding for Stable Alignment
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Solution Overview
Problem
Conventional transflective liquid crystal display (LCD) panels face issues with liquid crystal molecule alignment due to high operating voltages, particularly where gate lines overlap major slits, leading to irregular arrangements and reduced liquid crystal effect.
Innovation Solution
The design incorporates an array substrate with gate lines that do not overlap major slits or are shielded by transparent electrode portions, ensuring stable liquid crystal molecule alignment through the use of parallel gate, common, and data lines defining subpixels with separate reflective and transmission regions, and a color filter substrate with alignment protrusions to maintain consistent liquid crystal layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the major slits are positioned to separate reflective and transmission regions, then the liquid crystal alignment is improved, but the gate line voltage causes irregular liquid crystal molecule arrangement in overlapping regions
Solution Approach 1:
The patent extracts the gate line from the overlapping region with the major slit by repositioning the major slit to a location that does not overlap with the gate line. This separation removes the harmful voltage effect from the liquid crystal alignment area while maintaining the functional separation between reflective and transmission regions.
Solution Approach 2:
The patent introduces a non-overlapping configuration as an intermediary solution between the major slit (which needs to separate regions) and the gate line (which provides voltage control). By positioning the major slit in a location that does not overlap with the gate line, the harmful voltage effect is mediated away from the liquid crystal alignment zone.
2Productivity
If the gate lines operate at high voltage to drive the display, then the display capability is enhanced, but the liquid crystal molecules become irregularly arranged in regions affected by the voltage
Solution Approach 1:
The patent extracts the liquid crystal molecules from the high-voltage affected region by positioning the major slit such that it does not overlap with the gate line. This removes the liquid crystal molecules from the harmful voltage zone while maintaining their functional role in the display regions.
Solution Approach 2:
The patent applies local quality by creating different electrical environments in different regions. The gate line operates at high voltage in its designated area to provide driving capability, while the major slit is positioned in a region free from voltage overlap to maintain stable liquid crystal alignment. This local differentiation allows both high display capability and stable molecular arrangement.
3Device complexity
If the major slits overlap with gate lines to simplify the structure, then the device complexity is reduced, but the liquid crystal effect is reduced due to irregular molecule arrangement
Solution Approach 1:
The patent extracts the major slit from the overlapping position with the gate line to eliminate the harmful interaction. Although this requires careful positioning design, it removes the source of irregular liquid crystal arrangement and maintains reliable liquid crystal effect in the display regions.
Solution Approach 2:
The patent resolves the conflict by considering the spatial dimension and positioning the major slit in a location that is offset from the gate line in the planar arrangement. This dimensional consideration allows both structures to coexist without overlap, maintaining both structural simplicity and liquid crystal reliability.
Data Source
AI summary
The invention provides an LCD panel with main slits corresponding to alignment protrusions. The gate lines are shielded by the electrode portion and do not overlap the main slits. Because the gate line and the major slits do not overlap, the liquid crystal molecule arrangement of the liquid crystal layer is not affected by the operating voltage of the gate line.