Transformed Geometry Cache for Tile-Based Rasterization Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Tile-based rendering (TBR) graphics processing systems that use untransformed display lists (UDLs) require multiple transformations of geometry data, leading to inefficiencies due to the need for complex caching and partial fetching of primitives, which can result in underutilized SIMD processor lanes and increased processing time.
Innovation Solution
Implementing a cache system that stores transformed primitive blocks, where untransformed primitives are grouped into blocks based on their transformed geometry data, allowing efficient caching and reuse across multiple tiles, thereby optimizing SIMD lane utilization and reducing transformation overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If untransformed display lists are used to store geometry data, then memory bandwidth requirements are reduced, but multiple transformations of geometry data are required leading to increased processing time
Solution Approach 1:
The geometry data is transformed in advance during the geometry processing phase and stored in the cache before the rasterization phase begins. This preliminary transformation eliminates the need for multiple transformations during rendering, reducing processing time while maintaining the memory bandwidth benefits of tile-based rendering.
2Loss of time
If transformed geometry data is cached for each tile, then transformation overhead is reduced, but complex caching mechanisms are required increasing device complexity
Solution Approach 1:
The rendering space is divided into tiles, and the cache is organized to store transformed geometry data specifically for each tile. This segmentation allows simple, tile-based caching logic that reduces transformation overhead without requiring complex global caching mechanisms, as each tile independently manages its own transformed geometry data.
3Quantity of substance
If primitives are partially fetched for each tile, then memory usage is optimized, but SIMD processor lanes become underutilized reducing productivity
Solution Approach 1:
Transformed geometry data is prepared and stored in the cache during the geometry processing phase before rasterization begins. This preliminary preparation ensures that when primitives are fetched during rendering, the complete transformed data is already available, allowing full utilization of SIMD processor lanes without requiring partial fetching operations.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primitive block; in response to receiving a request to add a new transformed primitive block to the cache when the cache is full, select a transformed primitive block to evict from the cache based on the counters associated therewith; and evict the selected transformed primitive block from the cache.