Transformed Indexes for Cache Line Overlap Reduction
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Solution Overview
Problem
In Asymmetric Multi-Processor systems with shared system level caches, cache line overlaps lead to conflict misses due to locality in processor memory transactions, resulting in reduced system performance.
Innovation Solution
Implementing a transformation function module that generates unique transformed indexes for each processor, scattering cache entries throughout the cache to prevent overlaps, and using processor-specific transformation functions to allocate cache lines based on these transformed indexes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache lines are allocated based on contiguous memory addresses using standard indexing, then memory transactions characterized in locality are efficiently served, but cache line overlaps occur leading to conflict misses and reduced system performance
Solution Approach 1:
The patent applies asymmetry by introducing processor-specific transformation functions that treat identical index values differently for different processors. Each processor's memory transactions are transformed using its unique function, causing transactions that would normally map to the same cache lines to be scattered to different locations. This asymmetric treatment resolves the conflict between serving local transactions efficiently and preventing cache line overlaps.
Solution Approach 2:
The patent changes the indexing parameter from direct memory address mapping to transformed index values. By applying transformation functions to the index parameter, the system alters how memory addresses map to cache lines. This parameter transformation ensures that transactions with locality characteristics are still served efficiently while their transformed indexes prevent overlaps with other processors' transactions.
2Adaptability or versatility
If a shared system level cache is used to accommodate multiple processor cores, then cache utilization is improved, but cache line overlaps between different processors increase causing conflict misses
Solution Approach 1:
The transformation function acts as an intermediary between the processor's memory transactions and the shared cache. This intermediary layer transforms the original indexes before cache lookup, preventing direct conflicts while maintaining the shared cache structure. The transformation function mediates between multiple processors' access patterns, ensuring that each processor's transactions are appropriately distributed across the shared cache space.
Solution Approach 2:
By assigning unique transformation functions to different processors, the system creates asymmetric access patterns in the shared cache. This asymmetry allows the cache to be shared effectively while preventing the harmful overlaps that would occur with symmetric, identical indexing. Each processor experiences the shared cache differently through its unique transformation function.
3Ease of operation
If rigid or flexible partitioning of cache space is used to accommodate different processor cores, then processor needs are met, but cache line overlaps and conflict misses still occur due to locality characteristics
Solution Approach 1:
The patent replaces static cache partitioning with dynamic, on-the-fly transformation of indexes. Instead of rigidly assigning fixed cache regions to processors, the system dynamically transforms each processor's indexes using its unique function, allowing flexible accommodation of different processor needs while preventing overlaps. This dynamic approach adapts to each processor's locality patterns without requiring fixed partitions.
Solution Approach 2:
The system changes the indexing parameter dynamically based on which processor is accessing memory. Each processor's transactions are transformed using its specific function, creating processor-specific index mappings. This parameter change approach accommodates different processor characteristics and access patterns while preventing the conflict misses that would occur with static partitioning.
Data Source
AI summary
Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for reducing the likelihood of cache line overlaps in a multi-processor system having a shared memory cache. A transformation function module coupled to the shared memory cache is configured to transform an index associated with a cache operation associated with a processor of the plurality of processors using a transformation function to generate a transformed index. In embodiments, groups of one or more processors have different or unique transformation functions associated with them in order to decrease the tendency or likelihood of their respective cache lines in the shared memory cache to overlap. Other embodiments are also described and claimed.