Transformer Circuit for Reducing EMI in High Speed CMOS SERDES
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Solution Overview
Problem
High-speed SERDES transmitters generate common mode signal spurs due to differences in rise and fall edges, leading to EMI violations, which are difficult to address with current common mode choke technologies, especially at data rates above 20 Gbps, as they require high magnetic coupling coefficients not feasible with CMOS integrated circuits.
Innovation Solution
A circuit topology using two transformers with small magnetic coupling coefficients (0.2-0.5) and variable capacitances to equalize the rise and fall edges of differential signals, reducing common mode signal spurs without degrading differential signal integrity, implemented on a silicon die with planar transmission lines to minimize parasitic capacitance and maintain balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If common mode chokes with high magnetic coupling coefficient are used to filter common mode signals, then common mode signal reduction is effective, but differential signal insertion loss increases and integration on silicon die becomes infeasible
Solution Approach 1:
The patent changes the magnetic coupling coefficient parameter from the conventional high value (0.95) to a lower range (0.2-0.5). This parameter change enables effective common mode filtering while reducing differential signal insertion loss and allowing integration on silicon die using planar transformers without high permeability magnetic materials.
2Object-generated harmful factors
If common mode chokes with high magnetic coupling coefficient are used to filter common mode signals, then common mode signal reduction is effective, but integration on silicon die becomes infeasible
Solution Approach 1:
The patent replaces the conventional common mode choke structure (using high permeability magnetic materials and complex winding configurations) with planar transformers implemented using standard CMOS compatible planar transmission lines. This substitution enables integration on silicon die while achieving effective common mode filtering through optimized coupling coefficients.
3Reliability
If perfect balance is achieved in transformer implementation, then signal integrity is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent achieves sufficient balance by controlling the magnetic coupling coefficient within the range of 0.2-0.5, which is easier to implement with planar transformers on silicon die. This parameter range provides a practical balance between achieving adequate signal integrity and maintaining manufacturability using standard CMOS fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves over 10 dB reduction in common mode signal spurs while maintaining signal integrity, suitable for data rates up to 40 Gbps, without increasing differential signal insertion loss or introducing signal noise.
Implementation Method 1
A first transformer having a primary winding connected between the first circuit arm common node and the first output; and a secondary winding of the first transformer is connected between an output of the buffer of the second main cursor branch and ground
Data Source
AI summary
This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a post-cursor branch comprising a delay, an inverter and a series terminating resistance connected between the first input and a first circuit arm common node, and a main cursor branch comprising a buffer and a series terminating resistance connected between the first input and the first circuit arm common node. A first transformer has a primary winding connected between the first circuit arm common node and a first output and a secondary winding connected between an output of the buffer of the main cursor branch of the second arm and ground, with a capacitor and a resistor connected in series between the secondary winding and ground. A second transformer has a primary winding connected between the second circuit arm common node and a second output and a secondary winding connected between an output of the buffer of the main cursor branch of the first arm and ground, with a capacitor and a resistor connected in series between the secondary winding of the second transformer and ground.