Transformer-Coupled Clock Oscillator for Low Phase Noise
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Solution Overview
Problem
Conventional oscillators suffer from poor power supply rejection ratio, phase noise, and reliability issues due to direct current operating point mismatches and voltage swings exceeding supply limits, which affect the symmetry and stability of clock signals.
Innovation Solution
A complementary transformer-based oscillator design with a 1:2 inductance ratio transformer between the drain and gate sides of transistors, using pairs of PMOS and NMOS transistors to maintain symmetric waveforms and control voltage swings below the supply voltage, ensuring reliability and improved phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional VCO with cross-coupled differential topology is used, then the oscillation frequency can be controlled by input voltage, but the power supply rejection ratio deteriorates due to connection between gate and drain of transistors
Solution Approach 1:
The patent divides the oscillator circuit into separate gate bias network and drain circuit. The gate bias is generated through a dedicated bias network that is electrically isolated from the drain side, preventing direct connection between gate and drain. This segmentation eliminates the PSRR degradation issue while maintaining frequency control capability.
Solution Approach 2:
The patent introduces an intermediate bias network that acts as a mediator between the power supply and the gate. This bias network includes resistors and capacitors that filter and regulate the gate bias voltage, isolating the sensitive gate from power supply fluctuations and improving power supply rejection ratio.
2Reliability
If transformer based oscillators are used, then phase noise and frequency pushing are reduced, but reliability deteriorates because voltages swing around DC level and may break transistor limits
Solution Approach 1:
The patent employs asymmetric voltage swing control where the gate voltage swings around a biased operating point that is offset from the supply rail, while the drain voltage swings are constrained within safe limits. This asymmetric biasing ensures that neither the gate nor drain voltages exceed transistor breakdown limits, improving reliability while maintaining low phase noise through proper oscillator design.
3Reliability
If conventional VCO topology is used, then frequency control is achieved, but DC operating point stability deteriorates due to silicon mismatches
Solution Approach 1:
The patent implements a feedback mechanism through the bias network that continuously monitors and adjusts the gate bias voltage to maintain a stable DC operating point. The bias network uses resistors and capacitors configured to provide negative feedback, compensating for variations due to silicon mismatches and ensuring stable oscillation conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved phase noise, power efficiency, and reliability by maintaining symmetric waveforms and controlling voltage swings within safe limits, enhancing the overall performance of clock signal generation in electronic devices.
Implementation Method 1
a first inductive element and a second inductive element that are magnetically coupled to each other
Data Source
AI summary
Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.