Transformer Deep Learning for Outlier IC Detection
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Solution Overview
Problem
Conventional methods for detecting outlier ICs in semiconductor manufacturing, such as wafer-level voltage stress test, D-PAT, and NNR, are inefficient and inaccurate, leading to increased costs and defective semiconductor dies.
Innovation Solution
The use of a transformer deep learning-based method for outlier IC detection, which involves operating multiple test items on ICs to generate measured values, selecting target and neighboring ICs, and executing a transformer deep learning model to predict values and identify outliers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer-level voltage stress test is used to detect outlier ICs, then detection capability is provided, but manufacturing cost increases due to specialized equipment and time requirements
Solution Approach 1:
The patent replaces the mechanical/electrical voltage stress test system with a data processing system using pre-trained machine learning models. Instead of applying physical voltage stress to ICs, the system uses test parameter data combined with wafer map data and pre-trained models to predict and identify outlier ICs, eliminating the need for specialized stress test equipment and reducing manufacturing costs while maintaining detection capability
Solution Approach 2:
The patent applies pre-trained machine learning models (trained on historical wafer test data) to new test data before final IC classification. The pre-training phase captures patterns and relationships in the data, enabling accurate outlier detection during production without requiring complex real-time analysis equipment, thus reducing both equipment costs and testing time
2Ease of operation
If D-PAT method is used for outlier detection, then screening process is simplified, but detection accuracy deteriorates due to ignoring correlations between test parameters
Solution Approach 1:
The patent merges test parameter data with wafer map data (spatial information) and combines multiple pre-trained models (e.g., gradient boosting decision tree, convolutional neural network, transformer) to create a comprehensive analysis system. This integration captures correlations between different test parameters and spatial relationships on the wafer, significantly improving detection accuracy while maintaining operational simplicity through automated processing
Solution Approach 2:
The patent uses an ensemble of multiple pre-trained machine learning models with different architectures (gradient boosting decision tree, convolutional neural network, transformer) to detect outlier ICs. Each model captures different patterns and relationships in the data, and their combined predictions provide more accurate and robust outlier detection compared to any single model, while the system remains easy to operate through automated ensemble processing
3Device complexity
If NNR method is used for outlier detection, then computational complexity is reduced, but detection accuracy deteriorates due to limited consideration of local neighborhood measurements
Solution Approach 1:
The patent extends the analysis from simple local neighborhood comparisons to multi-dimensional analysis by combining test parameter values with wafer map spatial coordinates and applying multiple pre-trained models that capture complex patterns. This multi-dimensional approach (combining parameter space, spatial space, and model ensemble space) dramatically improves detection accuracy while the pre-trained nature of the models keeps computational complexity manageable during production
Data Source
AI summary
In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.