Transformer Network for Digital IC Path Delay Prediction
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Solution Overview
Problem
Current methods for timing analysis in digital integrated circuits face challenges in accurately predicting path delays before routing, leading to timing inconsistencies and inefficient design processes due to inaccurate estimation and high computational complexity.
Innovation Solution
A post-routing path delay prediction method that uses a transformer network to capture timing and physical correlations between cells, preprocessing data to form feature sequences, and performing dimension reduction to predict path delays before routing, thereby guiding circuit design and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional mathematical model-based quick pre-routing timing estimation methods are used, then computing complexity is reduced, but prediction accuracy deteriorates because they ignore the influence of routing on cell delay and path delay
Solution Approach 1:
The patent replaces traditional mathematical model-based timing estimation with a machine learning model (XGBoost or neural network) that can capture complex non-linear relationships between routing configurations and timing parameters. This substitution allows the system to achieve higher accuracy without manually deriving complex mathematical models, effectively resolving the contradiction between accuracy and computational complexity.
Solution Approach 2:
The patent transforms the timing estimation problem by changing the input parameters from simple routing length/delay metrics to a comprehensive set of features including cell delay, path delay, routing length, and routing density. This parameter transformation enables the machine learning model to capture the intricate influence of routing on timing while maintaining computational efficiency through feature engineering rather than complex calculations.
2Measurement precision
If machine learning-based pre-routing timing estimation methods are used, then prediction accuracy improves, but computing complexity increases and error accumulation occurs due to accumulation of cell and net delay predictions
Solution Approach 1:
The patent extracts the essential timing information directly from post-routing static timing analysis results and uses it to train the machine learning model. By taking out the ground truth delay values and using them as training labels, the model learns to predict path delays without accumulating errors from multiple separate predictions. This extraction approach eliminates the error accumulation problem while maintaining high accuracy.
Solution Approach 2:
The patent performs preliminary action by conducting post-routing static timing analysis to obtain accurate delay values, which are then used to train the machine learning model. This preliminary acquisition of ground truth data allows the model to learn accurate timing relationships before they are needed for prediction, avoiding the error accumulation that would occur if predictions were made without such preliminary accurate measurements.
3Reliability
If pessimistic timing estimation strategy is used, then timing safety is improved, but over-optimization occurs resulting in waste of circuit area, power and design time
Solution Approach 1:
The patent implements feedback by using actual post-routing timing analysis results to train and validate the machine learning model. This feedback loop allows the model to learn from real timing data and provide accurate predictions that reflect actual circuit behavior. With accurate predictions, designers can make informed decisions about timing optimization without relying on pessimistic strategies, thereby avoiding waste of design time and resources while maintaining timing safety.
Data Source
AI summary
A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.