Transient Buffer for Cache Pollution Prevention
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Solution Overview
Problem
Conventional microprocessor architectures face challenges in minimizing the penalty of accessing higher level structures and prioritizing entries with high temporal locality within lower level structures, such as L1 caches, due to the installation of non-temporal entries which can evict useful entries and increase latency.
Innovation Solution
Implementing a transient buffer between higher and lower level structures, equipped with confidence logic circuitry to filter out less frequently used entries and selectively transfer only frequently accessed entries to the lower level structures, thereby reducing the penalty of accessing higher level structures and enhancing temporal locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If entries are installed into lower level structures (L1 cache) from higher level structures (L2 cache), then access speed is improved for frequently accessed entries, but non-temporal entries can evict useful entries and increase latency
Solution Approach 1:
The patent introduces a transient buffer as an intermediary structure between the L2 cache and L1 cache. This buffer temporarily holds incoming entries from L2 cache before they are selectively installed into L1 cache. The transient buffer acts as a mediator that filters out non-temporal entries (entries with low temporal locality) and prevents them from polluting the L1 cache, thereby avoiding unnecessary evictions of useful entries and reducing access latency while still allowing fast access to frequently accessed entries.
2Area of stationary object
If the L1 cache is kept small due to area constraints, then area usage is optimized, but useful entries can be evicted in favor of less useful entries from mispredicted paths
Solution Approach 1:
The transient buffer serves as a filtering intermediary that protects the small L1 cache from being polluted by non-temporal entries. By selectively installing only high-temporal-locality entries into L1 cache while discarding or deferring non-temporal entries, the transient buffer ensures that the limited L1 cache space is utilized efficiently for storing useful, frequently accessed entries, thereby maintaining high temporal locality despite the small cache size.
Solution Approach 2:
The patent changes the parameter of entry selection by introducing temporal locality assessment. Instead of installing all incoming entries from L2 cache into L1 cache, the system evaluates the temporal locality of each entry and selectively installs only those with high temporal locality. This parameter change in selection criteria ensures that the small L1 cache maintains high reliability in terms of temporal locality while keeping area constraints satisfied.
3Ease of operation
If victim cache is used to replace evicted blocks, then cache replacement is managed, but there is no circuitry to filter out less useful entries
Solution Approach 1:
The patent applies preliminary action by performing temporal locality assessment and filtering of entries before they are installed into the L1 cache. The transient buffer evaluates incoming entries from L2 cache in advance, determining their temporal locality characteristics before committing them to L1 cache. This preliminary filtering action prevents non-temporal entries from entering L1 cache in the first place, eliminating the need for complex filtering circuitry in the victim cache and simplifying the overall system while improving cache effectiveness.
Data Source
AI summary
A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.