Self-Reset Transient-to-Digital Convertor for ESD Immunity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits (ICs) face challenges in withstanding electrostatic discharge (ESD) stress due to their vulnerability as semiconductor processes advance, leading to increased costs from additional discrete noise-bypassing components required for system-level ESD immunity.
Innovation Solution
An on-chip transient-to-digital convertor with a transient detection circuit comprising a voltage drop unit, current amplifier unit, and time control unit generates digital codes corresponding to ESD voltages without additional discrete noise-bypassing components, utilizing an RC delay effect for auto-recovery after detecting an ESD pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional discrete noise-bypassing components (decoupling capacitor, TVS, current-limiting resistance) are used to improve system-level ESD immunity, then ESD protection capability is enhanced, but total cost of microelectronic products substantially increases
Solution Approach 1:
The patent extracts the ESD protection function from external discrete components and implements it within the IC chip itself through a dedicated transient detection circuit. This circuit includes voltage drop units, current amplifier units, and time control units that collectively provide ESD immunity without requiring external decoupling capacitors, TVS diodes, or current-limiting resistors, thereby eliminating the cost and complexity of additional discrete noise-bypassing components
Solution Approach 2:
The IC chip performs self-protection against ESD events through the integrated transient detection circuit. The circuit automatically detects ESD pulses, generates corresponding digital codes, and triggers protective actions without requiring external protection components. The self-service mechanism eliminates the need for additional discrete noise-bypassing components while maintaining system-level ESD immunity
2Productivity
If semiconductor processes advance toward deep sub-micron manufacturing with scaled-down devices and thinner gate oxides, then device integration and performance are improved, but vulnerability to ESD stress increases
Solution Approach 1:
The transient detection circuit is designed with multiple voltage drop units having different breakdown voltages that are predetermined during manufacturing. When an ESD event occurs, the appropriate voltage drop unit automatically conducts based on the ESD pulse amplitude, triggering the corresponding protection response before damage can occur to the sensitive deep sub-micron devices
Solution Approach 2:
The circuit employs feedback mechanisms where the conduction state of voltage drop units and current amplifier units generates digital codes that reflect the ESD stress level. This feedback information enables the system to adaptively respond to ESD events, providing enhanced protection for scaled-down devices with thinner gate oxides while maintaining high device integration and performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances system-level ESD immunity for CMOS ICs by converting transient voltages into digital codes to detect ESD events, issuing protect/warn signals without additional components, and automatically resetting to regular voltage, thereby reducing costs and improving immunity against electrical transient disturbances.
Implementation Method 1
executes an auto-recovery procedure in microelectronic systems based on RC delay effect after detecting an ESD pulse
Data Source
AI summary
A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.