Transient Pulse Detection Circuit for Memory Security
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Solution Overview
Problem
Memory circuits are vulnerable to unauthorized transient pulses on word lines, which can lead to unintended operations and data integrity issues, particularly during fault injection attacks.
Innovation Solution
A transient pulse detection circuit is integrated into the memory system, comprising a state detection circuit, state storage circuit, and state change detection circuit, which differentiate between authorized and unauthorized voltage changes on word lines using an end-of-operation signal to prevent unauthorized glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transient pulse detection circuit is integrated into the memory system, then data integrity and security are enhanced, but device complexity increases
Solution Approach 1:
The detection circuit is integrated within the existing memory system architecture, merging the security function with the memory control circuitry. The state detection circuit, state storage circuit, and state change detection circuit are combined into a unified detection mechanism that operates within the memory system, sharing resources and reducing overall system complexity despite adding functionality.
Solution Approach 2:
The patent introduces an intermediary end-of-operation signal that mediates between the memory operations and the detection circuit. This signal acts as a coordinator that enables the detection circuit to distinguish between authorized and unauthorized pulses without requiring direct integration with all memory operation circuits, thereby managing complexity through a controlled interface.
2Measurement precision
If the detection circuit uses an end-of-operation signal to differentiate authorized and unauthorized pulses, then measurement precision improves, but device complexity increases
Solution Approach 1:
The end-of-operation signal is generated in advance of potential unauthorized pulses, establishing a temporal reference frame before the detection phase begins. This preliminary signaling allows the detection circuit to be primed and configured for high-precision detection during critical periods without requiring continuous complex monitoring of all voltage changes.
Solution Approach 2:
The detection circuit operates in periodic cycles synchronized with the end-of-operation signal, alternating between detection phases and reset phases. This periodic operation allows the circuit to achieve high measurement precision during detection windows while reducing complexity during reset intervals, creating a rhythm that balances accuracy and resource usage.
3Reliability
If the detection circuit synchronizes with operational phases, then reliability improves, but loss of time increases
Solution Approach 1:
The detection circuit maintains continuous monitoring capability through overlapping detection and reset phases. While one phase is active, the other is preparing, ensuring that useful detection action is always ongoing. The end-of-operation signal triggers seamless transitions between phases, preventing gaps in security coverage and minimizing overall cycle time despite the dual-phase operation.
Data Source
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AI summary
The invention relates to a memory comprising at least one line (WLm) to which memory cells are connected. A control circuit is configured to emit a transient operation end signal (OPm) at the end of the execution of an operation in at least one memory cell, and a circuit for detecting a transient pulse (DC1) connected to the line (WLm) of the memory is configured to deliver a signal indicating a transient pulse has been detected when a falling front of the amplitude of a voltage signal (Csm) appears on the line of the memory in the absence of the operation end signal.