Transient Voltage Suppressor With Segmented Transistors for ESD Protection
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) events, and existing protection methods may not adequately prevent circuit damage during such events.
Innovation Solution
A transient voltage suppressor (TVS) is designed with N transistors and semiconductor units, including diodes or bipolar transistors, coupled between a reference ground and pads, which provides high impedance under normal conditions and low impedance during ESD events to divert ESD currents to the ground, utilizing a power clamp circuit to drain currents from the reference power line to the ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TVS is designed to provide low impedance during ESD events to divert ESD currents, then ESD protection capability is improved, but the device complexity increases due to the need for multiple transistors and semiconductor units
Solution Approach 1:
The TVS is divided into N first transistors and N semiconductor units, where each first transistor is associated with a corresponding semiconductor unit. This segmentation allows the TVS to provide low impedance paths at multiple locations simultaneously, improving ESD protection capability while maintaining a modular structure that manages complexity through repetition of standardized units.
Solution Approach 2:
The first transistors are controlled by a voltage on a reference power line to provide high impedance under normal conditions and low impedance during ESD events. The semiconductor units (diodes or second transistors) provide additional protection paths. This multi-functional design allows a single TVS structure to handle both normal operation and ESD protection, reducing the need for separate protection circuits and thereby managing overall device complexity.
2Reliability
If the TVS provides high impedance between operating voltage and reference ground during normal operation, then normal circuit operation is maintained, but the response speed to ESD events may be delayed
Solution Approach 1:
The first transistors are pre-configured with control connections to the reference power line, so that when an ESD event occurs, the transistors can immediately switch from high impedance to low impedance state. The semiconductor units are also pre-positioned to provide immediate additional protection paths. This preliminary configuration eliminates delays that would occur with slower detection and activation mechanisms, achieving both normal operation stability and fast ESD response.
3Reliability
If N transistors and N semiconductor units are used to provide comprehensive ESD protection, then ESD protection coverage is improved, but the manufacturing cost increases
Solution Approach 1:
The TVS uses N first transistors and N semiconductor units, where each unit can be independently fabricated using standard semiconductor manufacturing processes. This segmentation into repeatable modules allows for efficient mass production and reduces per-unit cost compared to custom-designed complex protection circuits. The modular structure enables standardized fabrication techniques to be applied across all N units.
Solution Approach 2:
The semiconductor units can be configured as either diodes or second transistors depending on the specific protection requirements. This flexibility in parameter selection allows optimization of the design for cost-effective manufacturing while maintaining comprehensive ESD protection coverage. The ability to choose between different semiconductor unit types enables selection of the most cost-effective implementation for each application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively protects circuits from ESD damage by rapidly diverting peak currents to the reference ground, ensuring normal operation and preventing ESD-induced damage.
Implementation Method 1
The TVS 110 sense the voltage levels of the operating voltage VPP and reference ground GND, and provides a very low impendence between the operating voltage VPP and reference ground GND. Such as that, a current IESD caused by the ESD event can be discharged to the reference ground GND
Implementation Method 2
each of the semiconductor units is a diode, wherein, a cathode of each of the diodes is coupled to the corresponding pad, and an anode of the each of the diodes is coupled to the reference ground
Implementation Method 3
The power clamp circuit drains a current from the reference power line to the reference ground when the transient voltage suppressor is operated in an electrostatic discharge (ESD) protection mode
Data Source
AI summary
The invention provides a voltage regulator including a transient voltage suppressor. The transient voltage suppressor includes N first transistors and N semiconductor units. The N first transistors are coupled between a reference ground and N pads respectively, and the N transistors are controlled by a voltage on a reference power line. The N semiconductor units are coupled between the reference ground and the N pads respectively, or coupled between the reference power line and the N pads respectively. N is a positive integer.