Transimpedance Amplifier Inductor Stacking for Area Reduction
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Solution Overview
Problem
Conventional transimpedance amplifiers face challenges in reducing surface area due to parasitic capacitance between adjacent negative feedback and gate inductors, which increases the occupied area on the substrate, making it difficult to achieve a reduction in surface area.
Innovation Solution
The transimpedance amplifier design involves forming the negative feedback and gate inductors in different wiring layers of a substrate with multiple layers, allowing them to be at least partially overlapped, which reduces the occupied area and minimizes parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the negative feedback inductor and gate inductor are formed adjacent to each other on the substrate, then the layout is simple, but the parasitic capacitance between the inductors increases and the occupied area increases
Solution Approach 1:
The patent applies three-dimensional stacking by forming the negative feedback inductor and gate inductor in different wiring layers (first wiring layer and second wiring layer) of the substrate. This vertical arrangement allows the inductors to be partially or fully overlapped in plan view, transforming the horizontal adjacency problem into a vertical stacking solution. The overlapping configuration in different layers reduces the occupied area on the substrate while maintaining electrical isolation through the substrate structure.
2Object-affected harmful factors
If the distance between the negative feedback inductor and gate inductor is increased to reduce parasitic capacitance, then the parasitic capacitance decreases, but the occupied area on the substrate increases
Solution Approach 1:
The patent resolves this contradiction by moving the inductors to different wiring layers, allowing them to overlap in the horizontal plane without creating parasitic capacitance issues. The vertical separation through the substrate layers provides electrical isolation while the overlapping horizontal projection minimizes the occupied area. This dimensional transformation allows close horizontal positioning without the parasitic capacitance penalty that would normally result from adjacent placement.
Solution Approach 2:
The patent implements nesting by placing the negative feedback inductor and gate inductor in different wiring layers such that they are partially or fully overlapped in plan view. The inductors are nested vertically within the multi-layer substrate structure, allowing one inductor to be positioned above the other in the vertical dimension while occupying the same or overlapping horizontal space. This nesting approach minimizes the total occupied area while maintaining electrical isolation.
3Area of stationary object
If the negative feedback inductor and gate inductor are formed in different wiring layers with overlapping planar projection, then the occupied area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by employing multiple wiring layers in the substrate. The negative feedback inductor is formed in a first wiring layer while the gate inductor is formed in a second wiring layer, with their planar projections partially or fully overlapping. This vertical stacking approach reduces the occupied area on the substrate. The substrate's multi-layer structure provides the necessary electrical isolation and routing paths, managing the manufacturing complexity through standardized multi-layer PCB or integrated circuit fabrication techniques.
Data Source
AI summary
A negative feedback inductor and a gate inductor are formed in different wiring layers of a substrate so as to be at least partially overlapped with each other in a plan view. When the lower wiring layer is thinner and the upper wiring layer is thicker, the negative feedback inductor Lc is formed in the lower wiring layer that is thinner.