Transistor Active Area Jog Layout for Uniform Silicide
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Solution Overview
Problem
In integrated circuit fabrication, the joining of transistors with different widths sharing a common active area leads to non-uniform active area overlap, resulting in increased series resistance and poor silicide formation, especially in scaled-down technologies where photolithographic effects cause significant variations in channel width, and the use of epitaxial stress enhancement techniques like SiGe or SiC often result in faceting and excessive diode leakage.
Innovation Solution
The implementation of an active geometry with a wide active region and a narrow active region having at least one jog where the wide active region transitions to the narrow active region, with a gate overlapping the jog, which minimizes the impact of photolithographic effects on channel width and allows for uniform series resistance and silicide formation, and eliminates active jogs in source and drain regions to prevent faceting during epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors with different widths share a common active area to reduce area and cost, then area efficiency improves, but active area overlap becomes non-uniform causing increased series resistance
Solution Approach 1:
The common active area is segmented into a first active area for the first transistor and a second active area for the second transistor, with the second active area having a different width than the first. This segmentation allows each transistor to have its own dedicated active region while sharing the common active area, ensuring uniform active area overlap for each transistor and preventing increased series resistance.
2Area of stationary object
If transistors with different widths share a common active area, then area efficiency improves, but silicide formation quality deteriorates
Solution Approach 1:
The common active area is divided into separate first and second active areas with different widths, allowing each transistor to have uniform active area overlap. This uniformity ensures proper silicide formation quality for both transistors while maintaining area efficiency through the shared common active area structure.
3Area of stationary object
If jog is placed close to gate in scaled-down technologies, then area efficiency improves, but photolithographic effects cause significant channel width variation
Solution Approach 1:
The active area is segmented into first and second active areas with different widths, positioned at different locations relative to the gate. This segmentation allows the jog to be placed optimally for area efficiency while each transistor's dedicated active area maintains uniform overlap, reducing photolithographic effects on channel width.
4Area of stationary object
If active jogs are present in source and drain regions, then area efficiency improves, but faceting occurs during epitaxial growth causing excessive diode leakage
Solution Approach 1:
The active area is segmented into first and second active areas, allowing the jog to be positioned in the common active area rather than in the source and drain regions of individual transistors. This eliminates faceting during epitaxial growth and excessive diode leakage while maintaining area efficiency through the shared common active area.
Data Source
AI summary
An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.