Transistor Active Region Recessing Reduction via Spacer Removal
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Solution Overview
Problem
The fabrication of transistors with critical dimensions of 40 nm and less faces issues such as significant yield loss and reduced performance due to deposition-related irregularities and recessing in the active regions, particularly when using high-stressed dielectric materials and high-k gate dielectric materials in advanced semiconductor devices.
Innovation Solution
The formation of drain and source extension regions using a protective liner material reduces recessing and allows for efficient deposition of interlayer dielectric materials, eliminating the need for offset spacers and reducing material loss, thereby enhancing transistor performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-stressed dielectric materials are deposited in close proximity to gate electrode structures, then transistor performance is enhanced through stress-induced mobility improvement, but deposition-related irregularities occur due to insufficient space
Solution Approach 1:
The method performs preliminary actions by forming drain and source extension regions before depositing the interlayer dielectric material. This preliminary formation of extension regions creates additional space that prevents deposition irregularities while maintaining the stress-induced mobility enhancement benefits
Solution Approach 2:
The method extracts the offset spacer component from the traditional process flow. By removing the offset spacer and using extension regions formed through selective epitaxial growth, the patent eliminates the need for additional spacer materials while achieving the same or better performance
2Manufacturing precision
If offset spacers are used to form drain and source extension regions, then lateral offset control is achieved, but material loss and active region recessing occur
Solution Approach 1:
The method employs selective epitaxial growth to form extension regions that self-align with the gate electrode structure. The epitaxial growth process automatically conforms to the underlying structure, providing self-aligned lateral offset control without requiring additional offset spacer materials
Solution Approach 2:
The method changes the formation mechanism from spacer-based physical offset to epitaxial growth-based controlled expansion. By adjusting epitaxial growth parameters (temperature, pressure, gas flow, growth rate), precise lateral offset control is achieved without the material loss associated with spacer deposition and removal
3Speed
If channel length is reduced to increase operating speed, then transistor switching speed improves, but dopant profile control becomes more difficult
Solution Approach 1:
The method replaces traditional ion implantation-based dopant introduction with in-situ dopant diffusion during selective epitaxial growth. This substitution provides better dopant profile control for short channel transistors by allowing precise control of dopant concentration and depth through epitaxial growth parameters rather than relying on implantation energy and angle control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in superior transistor characteristics with reduced series resistance and increased space between gate electrode structures, minimizing deposition-related irregularities and improving overall production yield and performance.
Implementation Method 1
The formation of drain and source extension regions using a protective liner material reduces recessing
Implementation Method 2
allows for efficient deposition of interlayer dielectric materials
Data Source
AI summary
Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.