Transistor Array Panel Contact Hole Etching via Single Mask

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Solution Overview

Problem

Conventional transistor array panel manufacturing processes require highly selective etching agents and multiple photomasks to create contact holes, increasing costs and complexity, and causing damage to the semiconductor layer.

Innovation Solution

A method for forming contact holes in a transistor array panel using a single mask and low to medium selectivity etching agents, allowing for simultaneous etching of multiple contact holes in different materials and depths without damaging the semiconductor layer, and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If highly selective etching agents and multiple photomasks are used to form contact holes, then manufacturing precision is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvecontact hole formation precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple etching operations into a single simultaneous etching process. Multiple contact holes at different depths and in different materials are etched at the same time using one etching agent, eliminating the need for multiple separate etching steps and multiple photomasks. This merging of operations reduces process complexity while maintaining the precision needed for different contact hole requirements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs a universal etching agent that can etch multiple different materials (such as silicon oxide, silicon nitride, and other insulating layers) with appropriate selectivity ratios. This single etching agent performs the function of what would traditionally require multiple specialized etchants, simplifying the manufacturing process while achieving the necessary precision for various contact hole formations across different layers.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If highly selective etching agents are used to form contact holes, then manufacturing precision is improved, but manufacturing cost increases

Engineering Contradiction:
Improvecontact hole formation precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges multiple expensive specialized etching agents into a single etching agent system. By using one etching agent to perform multiple etching tasks that would traditionally require several different high-selectivity agents, the patent reduces material costs while maintaining the precision needed for forming contact holes through different insulating layers with different etching rates.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If conventional etching processes are used to form contact holes, then contact holes can be formed, but damage to the semiconductor layer occurs

Engineering Contradiction:
Improvecontact hole formation efficiencyVSAvoidsemiconductor layer damage
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality control by using an etching agent system where different regions or layers are etched at different rates based on their material properties. The etching process is selectively controlled to remove insulating layers while preserving the semiconductor layer, achieving the needed etching depth and precision without causing damage to sensitive semiconductor regions through careful selection of etching chemistry and process parameters.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11183518B2Transistor array panel and manufacturing method thereof
Publication Date: 2021.11.23 SAMSUNG DISPLAY CO LTD
  • US11183518B2 patent drawing
  • US11183518B2 patent drawing
  • US11183518B2 patent drawing

AI summary

A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.