Select Transistor Body Bias for Fuse Programming
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Solution Overview
Problem
Electrically programmable fuses require significant current and higher voltages for programming, leading to larger transistors and potential 'write disturb' issues, where logic states can be accidentally changed during programming.
Innovation Solution
The use of a parasitic bipolar transistor bias on the body of select transistors to increase current carrying capability without increasing transistor size, allowing for reduced programming voltage and preventing accidental programming by applying a switchable body bias of 0.7 volts during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If electrically programmable fuses are programmed using conventional methods, then programming can be achieved, but significant current and higher voltages are required leading to larger transistors
Solution Approach 1:
The patent applies parameter changes by utilizing body bias voltage modification to alter the transistor's current carrying capability. By applying a body bias of approximately 0.7 volts during programming operations, the transistor's threshold voltage changes, enabling higher current flow through the same physical device without increasing its size. This resolves the contradiction by changing the electrical parameters rather than the physical dimensions.
Solution Approach 2:
The patent implements dynamics by making the transistor's operating characteristics adjustable through body bias control. The body bias voltage can be dynamically changed between different values (e.g., 0 volts for normal operation, 0.7 volts for programming), allowing the transistor to adapt its current carrying capability based on the operational mode. This dynamic adjustment enables high programming current through a standard-sized transistor.
2Power
If higher voltages are applied to pass high currents for fuse programming, then programming can be achieved, but the voltages are higher than the power supply voltage used to power logic transistors
Solution Approach 1:
The patent uses parameter changes by modifying the body bias voltage to achieve the required programming conditions. Instead of applying significantly higher voltages to the drain-source terminals, the invention changes the body bias parameter to approximately 0.7 volts, which modifies the transistor's I-V characteristics and enables high current flow at manageable voltage levels. This reduces the complexity of voltage control compared to conventional high-voltage programming methods.
3Area of stationary object
If electrically programmable fuses are placed on the same word line or bit line as the one being programmed, then space is saved, but logic state changes can occur in other fuses
Solution Approach 1:
The patent applies local quality by creating different operational conditions for different parts of the memory array during programming. By applying body bias only to the select transistor involved in the programming operation, while other transistors remain at their normal bias conditions, the invention creates a localized high-current path for programming while preventing widespread logic state changes. This allows dense placement of fuses while maintaining reliability.
Solution Approach 2:
The patent implements preliminary anti-action by using body bias control to prevent unwanted programming operations before they can occur. By carefully controlling which transistor receives the body bias during programming, the invention preemptively prevents current from flowing through other fuses on the same word or bit line, thereby preventing accidental logic state changes before they can happen.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming margin, reduces transistor size, and minimizes accidental programming by increasing current carrying capacity while maintaining lower voltages, thus improving efficiency and preventing 'write disturb' in electrically programmable fuses.
Implementation Method 1
The current provided is current limited so that the parasitic transistor carries a very small percentage of the current required for programming the fuses
Implementation Method 2
providing a bias on the body of transistors that is limited by a parasitic bipolar transistor formed by the channel as the base, the source as the emitter, and the drain as the collector
Implementation Method 3
electrically programmable fuses that are on the same word line or bit line as the one being programmed
Data Source
AI summary
An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells including a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse.