Ferroelectric Transistor Fabrication With Defect-Free Channel Layer

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Solution Overview

Problem

Conventional methods for forming ferroelectric layers in transistors often damage the channel layer due to plasma bombardment, leading to defects and degradation in current on/off ratio, which compromises transistor performance.

Innovation Solution

A non-plasma deposition process is used to form the ferroelectric layer, reducing plasma-induced defects and allowing for subsequent annealing to remove defects, ensuring a substantially defect-free channel layer and improved transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If plasma deposition process is used to form ferroelectric layer, then deposition efficiency is improved, but channel layer is damaged due to plasma bombardment causing defects and degradation in current on/off ratio

Engineering Contradiction:
Improvedeposition efficiencyVSAvoidcurrent on/off ratio
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The harmful plasma bombardment component is extracted and removed from the deposition process. The patent specifically eliminates the plasma step while retaining the beneficial ferroelectric layer formation through non-plasma deposition methods, thereby preventing channel layer damage while maintaining deposition efficiency

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

An intermediary approach is introduced by using non-plasma deposition methods (such as atomic layer deposition or chemical vapor deposition) as a mediator between the need for efficient ferroelectric layer formation and the requirement to protect the channel layer from plasma-induced damage

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If plasma deposition process is used, then ferroelectric layer formation is achieved, but defects are introduced in channel layer leading to performance degradation

Engineering Contradiction:
Improveferroelectric layer formationVSAvoidchannel layer defect density
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent converts the harmful effect of plasma by completely avoiding its use. Instead of trying to mitigate plasma damage, the invention adopts non-plasma deposition techniques that inherently prevent channel layer damage while still achieving high-quality ferroelectric layer formation, thus turning the potential harm into a benefit by eliminating the source of damage

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents degradation of the current on/off ratio and ensures the performance of the second transistor by reducing defects and enhancing the integrity of the channel layer.

Implementation Method 1

A non-plasma deposition process is used to form the ferroelectric layer, reducing plasma-induced defects

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

allowing for subsequent annealing to remove defects, ensuring a substantially defect-free channel layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS11862726B2Transistor, integrated circuit, and manufacturing method of transistor
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862726B2 patent drawing
  • US11862726B2 patent drawing
  • US11862726B2 patent drawing

AI summary

A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.