Transistor Channel Design for Leakage Reduction
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Solution Overview
Problem
As transistors in integrated circuits (ICs) scale down, manufacturing variability leads to electronic mismatch between transistors, causing leakage and degrading device performance due to impurities, non-uniform doping, and processing variations, which results in poor gate control and reduced yield.
Innovation Solution
A transistor channel configuration is introduced, featuring a delta-doped layer with a peak retrograde dopant concentration, a carbon-containing layer to prevent back diffusion, and a counter-doped layer to reduce leakage, along with a substrate layer for a steep dopant profile, improving matching between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to continue Moore's Law, then transistor density and integration capacity improve, but manufacturing variability increases causing electronic mismatch between transistors
Solution Approach 1:
The patent applies local quality by implementing a halo implant that creates localized high-doping regions specifically at the source and drain junctions of each transistor. This localized doping adjustment compensates for local manufacturing variations without affecting other transistors, thereby improving electronic matching while maintaining high transistor density.
Solution Approach 2:
The patent employs parameter changes by adjusting the doping concentration parameters in the channel region through halo implant. By modifying the dopant concentration locally at source/drain junctions, the patent compensates for manufacturing variability and achieves better threshold voltage matching across scaled transistors.
2Object-generated harmful factors
If halo implant is used to reduce leakage between source and drain, then leakage current decreases, but local variations in substrate structure increase causing poor electronic matching
Solution Approach 1:
The patent uses local quality by confining the high-doping halo implant specifically to the source and drain junction regions. This localized approach reduces leakage current at critical interfaces while minimizing disruption to the overall substrate structure, thereby maintaining better electronic matching between transistors.
Solution Approach 2:
The patent applies skipping by using precise ion implantation techniques that rapidly deposit dopants only in the desired halo regions without causing extensive damage or variation in the surrounding substrate. This rushed, targeted doping approach reduces leakage while limiting local structural variations.
3Object-generated harmful factors
If channel doping concentration is increased to reduce leakage, then leakage between source and drain decreases, but threshold voltage control deteriorates
Solution Approach 1:
The patent applies local quality by implementing halo implant that increases doping concentration specifically at the source and drain junctions rather than uniformly throughout the channel. This localized high doping reduces leakage current at critical interfaces while preserving the doping profile in the channel region, thereby maintaining good threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electronic matching and reduces leakage, improving transistor performance and yield by mitigating local and global variations in dopant concentrations.
Implementation Method 1
a layer of carbon-containing material overlying the delta-doped layer and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate
Data Source
AI summary
Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.