Transistor Channel Shape Control for Leakage Reduction
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Solution Overview
Problem
In the development of transistors, controlling the work function of the gate electrode to reduce off-state leakage current and suppress gate-induced drain leakage (GIDL) current is challenging, leading to increased manufacturing costs and complexity due to the need for additional processing steps.
Innovation Solution
A transistor design where the semiconductor layer in the channel region has a shape that differs between the middle and end portions, allowing for localized control of the threshold voltage and reduced GIDL current by varying the width, taper, or height of the semiconductor layer, thereby increasing the threshold voltage and reducing off-state leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the work function of the gate electrode is controlled to reduce off-state leakage current, then the off-state leakage current is reduced, but another process is required which increases the number of processes and manufacturing cost
Solution Approach 1:
The patent applies local quality by creating a non-uniform semiconductor layer where the middle portion of the channel region has a different shape (larger cross-sectional area) than the end portions. This geometric variation locally modifies the electric field distribution and potential profile along the channel, enabling threshold voltage control without requiring additional gate electrode processing steps. The differentiated shape provides localized control of carrier concentration and electric field strength, achieving the desired reduction in off-state leakage current through structural design rather than additional manufacturing processes.
2Object-generated harmful factors
If the work function of the gate electrode is controlled to suppress GIDL current, then the GIDL current is suppressed, but another process is required which increases the number of processes and manufacturing cost
Solution Approach 1:
The patent suppresses GIDL current through local quality by designing the semiconductor layer with a differentiated shape along the channel length. The middle portion having a larger cross-sectional area creates a potential well that modifies the electric field distribution, reducing the high-field region at the drain end where GIDL current typically occurs. This geometric modification locally controls the electric field strength and carrier injection conditions, achieving GIDL suppression through structural design rather than additional gate electrode work function control processes.
3Productivity
If a three-dimensional transistor structure is used to achieve higher performance and further die shrink, then performance is improved, but it is difficult to stably control film thickness
Solution Approach 1:
The patent transitions from a two-dimensional planar transistor structure to a three-dimensional structure by creating a semiconductor layer with varying cross-sectional area along the channel length. The middle portion protrudes or has increased thickness compared to the end portions, adding a vertical/dimensional component to the channel structure. This dimensional change increases the effective channel width and control area without requiring extreme thinness control, thereby improving transistor performance while avoiding the film thickness control difficulties associated with ultra-thin planar structures.
Data Source
AI summary
[Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control.[Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.