Fin-Type Transistor Channel Stress Engineering
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Solution Overview
Problem
The reduction in feature size of metal oxide semiconductor (MOS) transistors leads to shorter channel lengths, increasing electric charge scattering and reducing mobility, which hinders the improvement of transistor saturation current.
Innovation Solution
Incorporating silicon carbide (SiC) or silicon germanium (SiGe) as lattice modifying materials in the channel layer of transistors, with epitaxial layers and specific structural configurations to enhance charge mobility, including fin-type active patterns and gate electrodes, to improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase device density, then the transistor saturation current is improved, but the charge mobility is reduced due to increased scattering
Solution Approach 1:
The patent changes the material composition parameter of the channel layer by incorporating silicon carbide (SiC) or silicon germanium (SiGe) to modify the lattice structure. This material parameter change induces stress in the channel, which alters the charge carrier mobility without requiring a change in channel length, thus resolving the contradiction between maintaining high saturation current and preserving charge mobility.
Solution Approach 2:
The patent uses composite material structures where the channel layer is formed with silicon carbide or silicon germanium mixed with silicon. This composite approach creates a strained silicon channel that enhances charge mobility through lattice mismatch-induced stress, allowing the device to achieve high saturation current even with reduced channel length.
2Reliability
If silicon carbide or silicon germanium is incorporated in the channel layer to increase charge mobility, then the operating performance is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the silicon carbide or silicon germanium layer before creating the final channel structure. The lattice modifying material is deposited first, then the channel layer is formed on top, which simplifies the overall manufacturing process compared to attempting to introduce stress after device fabrication. This sequential approach integrates stress engineering into the standard CMOS fabrication flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of silicon carbide or silicon germanium in the channel layer increases charge mobility, thereby enhancing the operating performance of transistors by applying tensile or compressive stress, improving saturation current and overall transistor efficiency.
Implementation Method 1
Incorporating silicon carbide (SiC) or silicon germanium (SiGe) as lattice modifying materials in the channel layer of transistors
Implementation Method 2
The use of silicon carbide or silicon germanium in the channel layer increases charge mobility, thereby enhancing the operating performance of transistors by applying tensile or compressive stress
Data Source
AI summary
Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.