Transistor Device With Confining Layer For Carrier Mobility
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Solution Overview
Problem
Conventional transistor fabrication methods result in low carrier mobility in the channel region due to ion diffusion during heating treatments, affecting device performance.
Innovation Solution
A confining layer, such as a germanium-silicon carbide (GeSiC) layer, is formed on a semiconductor substrate to confine impurity ions, preventing them from diffusing into an epitaxial silicon layer used as an intrinsic channel region, thereby improving carrier mobility and allowing impurity ions to function as carriers in inversion mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heating treatment is performed during transistor fabrication, then impurity ions are activated and device formation is completed, but impurity ions diffuse into the channel region causing low carrier mobility
Solution Approach 1:
The patent segments the semiconductor structure into distinct regions: a confining layer (first semiconductor layer) and an intrinsic channel region (second semiconductor layer). This segmentation prevents impurity ions from the substrate from diffusing into the channel region during heating treatment, thereby maintaining high carrier mobility while still allowing necessary thermal processing.
Solution Approach 2:
The confining layer acts as an intermediary barrier between the impurity-containing substrate and the intrinsic channel region. This intermediate layer blocks the diffusion path of impurity ions while permitting the thermal energy needed for device formation and activation, resolving the contradiction between heating requirements and mobility preservation.
2Ease of manufacture
If ion implantation is used to form well regions, then doping is achieved, but impurity ions contaminate the channel region reducing carrier mobility
Solution Approach 1:
The patent divides the semiconductor structure into a confining layer and an intrinsic channel region, physically separating the doping zone from the channel zone. This allows ion implantation to effectively dope the well regions through the confining layer while preventing impurity contamination of the channel region, maintaining both manufacturing ease and precision.
Solution Approach 2:
The confining layer serves as an intermediary that permits controlled ion transmission for well region formation while blocking excessive impurity diffusion into the channel region. This mediator enables effective doping without compromising channel region purity and carrier mobility.
3Device complexity
If no confining layer is used, then fabrication process is simpler, but impurity ions diffuse freely into the channel region
Solution Approach 1:
The confining layer is introduced as a necessary intermediary to prevent impurity diffusion into the channel region. While this adds structural complexity, it is essential for maintaining the intrinsic nature of the channel region and achieving high carrier mobility, thus resolving the trade-off between simplicity and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances carrier mobility in the channel region by preventing ion diffusion into the epitaxial silicon layer, improving transistor performance by maintaining the intrinsic nature of the channel region and utilizing confined impurity ions as carriers.
Implementation Method 1
confine impurity ions diffused from the semiconductor substrate to the confining layer
Data Source
AI summary
Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.