Transistor Contact-Hole Layout for Smaller Display Pixel Pitch
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Solution Overview
Problem
Existing electronic devices face challenges in achieving smaller sizes while maintaining high display quality and resolution, particularly in the design of transistors and their layout on substrates.
Innovation Solution
The electronic device incorporates a transistor structure with a semiconductor layer, gate insulating layer, and electrodes, where the minimum distance between the electrodes and the gate electrode is optimized to be less than the distance between the contact holes and the gate electrode, allowing for reduced transistor size and pitch between adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the transistor size is reduced to achieve smaller electronic device size, then the device size is reduced, but the manufacturing precision and electrode positioning accuracy become more difficult to maintain
Solution Approach 1:
The patent introduces a multi-layer structure with contact holes penetrating through the gate insulating layer, transitioning from a planar two-dimensional layout to a three-dimensional vertical structure. This allows electrodes to contact the semiconductor layer through the insulating layer, enabling smaller transistor footprints while maintaining adequate spacing between adjacent transistors for manufacturing precision.
Solution Approach 2:
The gate insulating layer serves as an intermediary element between the gate electrode and the semiconductor layer. Contact holes are formed through this insulating layer to enable electrical connection, allowing the electrode to be positioned at an optimal distance from the gate electrode while maintaining electrical connectivity, thus resolving the conflict between size reduction and positioning accuracy.
2Productivity
If the pitch between adjacent transistors is reduced to increase device integration, then the device density is improved, but the reliability and performance consistency become more difficult to maintain
Solution Approach 1:
The gate insulating layer is segmented with multiple contact holes (first contact holes and second contact holes) distributed across the structure. This segmentation allows for better distribution of electrical connections and stress management, enabling closer transistor spacing while maintaining performance consistency through improved current distribution and reduced localized stress.
Solution Approach 2:
The patent changes the structural parameters by forming contact holes through the gate insulating layer, which alters the electrical and mechanical parameters of the transistor structure. This parameter change enables reduced pitch between transistors while maintaining reliability through improved current flow characteristics and reduced parasitic effects.
Data Source
AI summary
An electronic device includes a substrate and a transistor disposed on the substrate. The transistor includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode and a second electrode. The gate insulating layer has first contact holes and second contact holes. The first electrode and the second electrode are disposed on the gate electrode and respectively contact the semiconductor layer through the first contact holes and the second contact holes. A minimum distance between a first side of the first electrode and the gate electrode is less than a minimum distance between a first edge of one of the first contact holes and the gate electrode, and a minimum distance between a first side edge of the semiconductor layer and the gate electrode is less than a minimum distance between the first edge of the one of the first contact holes and the gate electrode.