Thin-Film Transistor Contact Layout for Reduced Pixel Pitch
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Solution Overview
Problem
The challenge is to develop an electronic device with reduced size while maintaining high display quality, which existing technologies struggle to achieve due to limitations in transistor design and layout.
Innovation Solution
The electronic device incorporates a substrate with transistors featuring a semiconductor layer, gate insulating layer, gate electrode, first electrode, and second electrode, where the minimum distance between the electrode sides and the gate electrode is optimized to be less than the distance between the contact holes and the gate electrode, allowing for reduced transistor size and pitch between adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the transistor size is reduced to achieve smaller electronic device, then the device size is reduced, but the manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The gate insulating layer is formed with contact holes (first and second contact holes) before the gate electrode is deposited. This preliminary formation of contact holes with precise positioning establishes the foundation for subsequent electrode placement, ensuring that the source and drain electrodes align correctly with the semiconductor layer regions even as transistor dimensions are reduced
Solution Approach 2:
The gate insulating layer serves as an intermediary structure that contains the contact holes, which act as mediators for positioning the source and drain electrodes. The contact holes provide a physical and visual reference that guides the formation of electrodes at correct positions and distances from the gate electrode, resolving the alignment precision challenge in miniaturized transistors
2Productivity
If the pitch between adjacent transistors is reduced to achieve higher resolution display, then the display quality is improved, but the transistor design complexity increases
Solution Approach 1:
The transistor structure is segmented into distinct functional regions: the gate insulating layer with contact holes, the gate electrode, and the source/drain electrodes. This segmentation allows each component to be optimized and positioned independently, simplifying the overall layout process even at reduced pitch dimensions
Solution Approach 2:
Different regions of the transistor structure have different properties optimized for their specific functions: the gate insulating layer provides electrical isolation and defines contact regions, the gate electrode provides control, and the source/drain electrodes provide current paths. This local optimization enables compact design while maintaining functionality at high display resolutions
Data Source
AI summary
An electronic device includes a substrate and transistors disposed on the substrate. At least one of the transistors includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The gate insulating layer includes first contact holes and second contact holes. The gate electrode is disposed on the gate insulating layer. The first electrode is disposed on the gate electrode, has a first side away from the gate electrode, and contacts the semiconductor layer through the first contact holes. The second electrode is disposed on the gate electrode, has a second side away from the gate electrode, and contacts the semiconductor layer through the second contact holes. The first contact holes have first edges away from the gate electrode. A minimum distance between the first side and the gate electrode is less than a minimum distance between the first edge of one of the first contact holes and the gate electrode.