Integrated Power Transistor Contact Structure for Source Potential Measurement
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Solution Overview
Problem
Existing integrated power transistor circuits face challenges in accurately measuring the source potential of power transistor cells without occupying active chip area, as conventional methods require additional electrode structures that lead to increased chip area usage and potential measurement inaccuracies.
Innovation Solution
The design incorporates a contact structure with a first section within the cell array and a second section outside the array, where the first section is electrically connected to a doped region and an electrode structure, while the second section connects to an interface structure, allowing for precise measurement of source potential without additional electrode structures outside the cell array, thus minimizing active chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional electrode structures are added outside the cell array to measure source potential, then measurement capability is improved, but chip area is increased
Solution Approach 1:
The contact structure is designed to serve multiple functions: it acts as both a current connection path and a measurement node for source potential. By making the contact structure itself measurement-capable, the patent eliminates the need for separate dedicated measurement electrodes, thereby achieving multi-functionality without increasing chip area.
Solution Approach 2:
The patent combines the current connection function and the measurement function into a single integrated contact structure. Instead of having separate electrodes for current flow and potential measurement, the same contact structure performs both roles, merging previously separate functions into one unified element.
2Measurement precision
If electrode structures are placed outside the cell array, then source potential can be measured, but active chip area is reduced
Solution Approach 1:
The contact structure within the cell array is designed to simultaneously serve as a current connection and a measurement node. This multi-functional design allows source potential measurement without requiring dedicated space outside the active cell array, thus maintaining high active chip area utilization.
Solution Approach 2:
The patent utilizes the vertical dimension and existing layer structure within the cell array to accommodate measurement functionality. By using the contact structure that already exists in the vertical stacking of the transistor, the measurement function is added without expanding the horizontal footprint, effectively using another dimension (vertical integration) to solve the area conflict.
Data Source
AI summary
A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.