3D Transistor Contact Structure for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices scale down, the reduced contact area leads to increased contact resistance, which affects the performance and efficiency of non-planar transistors, necessitating enhanced contact area optimization.
Innovation Solution
The enhancement of transistor contact area is achieved through the use of a blanket dopant, semiconductor-on-insulator (SOI), and pocket channel dopant (PCD) structures, which increase the contact area by utilizing available real estate and reducing sub-fin leakage, thereby alleviating contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase density, then capacity increases, but contact area decreases leading to increased contact resistance
Solution Approach 1:
The patent extends the contact region from a single-plane surface contact to a multi-dimensional structure by forming contacts at multiple depths and lateral positions within the fin structure. This includes top surface contacts, sidewall contacts, and bottom contacts, effectively utilizing three-dimensional space to increase total contact area without increasing the planar footprint, thereby maintaining high device density while improving contact reliability
Solution Approach 2:
The contact structure is nested within the fin structure itself, with conductive contacts formed at multiple levels: top contacts on the fin top surface, sidewall contacts embedded in the fin sidewalls, and bottom contacts at the fin base. This nested arrangement allows contacts to be integrated within the existing fin geometry, maximizing contact area utilization without requiring additional external space
2Reliability
If non-planar transistors are used to maintain performance at smaller scales, then device performance is maintained, but contact area is further reduced
Solution Approach 1:
The contact system is segmented into multiple independent contact regions distributed throughout the fin structure: top surface contacts, sidewall contacts at various heights, and bottom contacts. Each segment contributes to the total contact area, and the segmented approach allows optimization of each contact region independently while collectively achieving the desired total contact area and performance
Solution Approach 2:
The patent transitions from two-dimensional planar contacts to three-dimensional contacts by utilizing the vertical dimension of the fin structure. Contacts are formed at multiple elevation levels including the top surface, intermediate sidewall positions, and the bottom of the fin, effectively converting a limited 2D contact problem into a 3D contact solution that maximizes area utilization
Data Source
AI summary
A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.