Transistor With Mismatched Crystal Orientation For Carrier Mobility
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Solution Overview
Problem
Conventional methods for forming transistors result in low saturation current due to insufficient carrier mobility, which affects device performance, especially as critical dimensions decrease and current leakage becomes a concern.
Innovation Solution
A method involving a semiconductor layer with a different crystal orientation than the substrate, where a dummy gate structure is formed, source and drain regions are created, and the semiconductor layer is non-crystallized and annealed to align crystal orientation with the substrate, followed by the formation of a metal gate structure with high K dielectric layers and spacers to enhance carrier mobility and reduce current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stress layer methods are used to promote carrier mobility, then carrier mobility is improved, but saturation current remains too low
Solution Approach 1:
The patent changes the crystal orientation parameter of the semiconductor layer from being parallel to the substrate to being at a different orientation (e.g., substrate at <100> and semiconductor layer at <110>). This parameter change creates stress between the layers that promotes carrier mobility while simultaneously enabling higher saturation current, resolving the contradiction between the two parameters.
Solution Approach 2:
The patent uses a composite structure consisting of a substrate and a semiconductor layer with different crystal orientations. This composite material approach allows the stress induced by the orientation mismatch to enhance carrier mobility in the channel region, while the overall device structure maintains high saturation current, thus resolving the contradiction.
2Productivity
If critical dimensions are decreased to improve device scaling, then device density is improved, but current leakage increases
Solution Approach 1:
The patent changes the crystal orientation parameter of the semiconductor layer to create stress that enhances carrier mobility. This allows the device to maintain high performance even at smaller critical dimensions, enabling better device density while the stress-induced mobility enhancement helps suppress short-channel effects and current leakage.
3Reliability
If stress layer is added to promote carrier mobility, then carrier mobility is improved, but device complexity increases
Solution Approach 1:
The patent merges the stress-inducing function with the semiconductor layer itself by using a semiconductor layer with different crystal orientation from the substrate. This eliminates the need for separate stress layer materials (such as silicon nitride), as the stress is inherently generated by the orientation mismatch between the substrate and the active semiconductor layer, thus reducing device complexity.
Solution Approach 2:
The semiconductor layer serves multiple functions: it acts as the active channel region for transistor operation and simultaneously serves as the stress-inducing layer due to its different crystal orientation. This multi-functionality eliminates the need for separate stress layer components, reducing overall device complexity while maintaining the carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases carrier mobility and saturation current by producing stress between the substrate and semiconductor layer, promoting device performance while minimizing current leakage through optimized metal gate spacer thickness and crystal orientation alignment.
Implementation Method 1
the semiconductor layer and the substrate having different crystal orientation... Stress is produced between the substrate and the semiconductor layer, whereby carrier mobility, and thus saturation current of the transistor, is raised
Implementation Method 2
annealing the channel layer so that the channel layer and the substrate have same crystal orientation
Data Source
AI summary
The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.