Transistor Die Layout Using Ancillary Elements for Higher Power
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Solution Overview
Problem
The challenge is to develop transistors that can achieve higher amplification levels without increasing the size of the semiconductor die, which is essential for keeping up with emerging cellular technologies like 5G while minimizing cost increments.
Innovation Solution
The solution involves integrating multiple transistor elements, including primary and ancillary transistor fingers, within a single semiconductor die, where ancillary transistor elements are placed in typically inactive regions of the die, enhancing power generation capability without increasing the die size. These elements are arranged in parallel and utilize through-substrate vias to minimize common-node inductance, allowing for higher power output within the same physical footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the semiconductor die is increased to achieve higher amplification levels, then the power generating capability is improved, but the manufacturing cost and device size increase
Solution Approach 1:
The transistor is divided into multiple independent transistor elements (first, second, third, and fourth elements) that are arranged in parallel within the semiconductor die. Each element has its own gate, source, and drain regions, allowing them to function independently while contributing collectively to the overall power output, thereby increasing power generating capability without proportionally increasing die size
Solution Approach 2:
Multiple transistor elements are merged into a single integrated transistor structure on one semiconductor die. The parallel arrangement of transistor elements combines their individual current handling capabilities to achieve higher overall power output while maintaining a compact form factor, resolving the contradiction between power and die size
2Power
If more transistor elements are integrated into the die to increase amplification, then the power output is improved, but the device complexity increases
Solution Approach 1:
Different regions of the semiconductor die are assigned different functions: active regions contain transistor elements for power generation, while inactive regions are utilized to house additional transistor elements. This local differentiation allows for increased complexity in specific areas without uniformly increasing overall device complexity, enabling higher amplification while managing structural complexity through spatial organization
Data Source
Figure 1~2A
Figure 2B~2C
Figure 3A
AI summary
A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.