Transistor With Dielectric Platform Reduces Gate-Drain Capacitance

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Solution Overview

Problem

Transistors face challenges in increasing power density while maintaining device breakdown voltage and effective heat removal, leading to limitations in performance and efficiency.

Innovation Solution

The design incorporates a trench structure with a dielectric platform and angled n-type doping to enhance current density and voltage breakdown, along with a fourth electrode to reduce parasitics and increase packing density, allowing for higher performance and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the physical size of the die is reduced to increase power density, then device performance and packing density improve, but device breakdown voltage and heat removal capability deteriorate

Engineering Contradiction:
Improvepower densityVSAvoiddevice breakdown voltage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a dielectric platform structure that extends vertically from the substrate surface, creating a three-dimensional architecture. This vertical dimension allows the transistor active region to be positioned over the platform, effectively increasing the breakdown voltage by adding vertical distance for voltage standoff while maintaining a compact horizontal footprint. The platform height provides an additional dimensional parameter to optimize both power density and breakdown voltage simultaneously.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The dielectric platform acts as an intermediary structure between the substrate and the transistor active region. This intermediate dielectric layer provides electrical isolation and voltage standoff, enabling the transistor to achieve higher breakdown voltage without increasing the horizontal die size. The platform mediates between the conflicting requirements of compact size and high voltage capability by providing a vertical isolation barrier.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the physical size of the die is reduced to increase power density, then packing density improves, but heat removal capability deteriorates

Engineering Contradiction:
Improvepower densityVSAvoidheat removal
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The dielectric platform creates vertical separation between the heat-generating transistor active region and the substrate, allowing for improved thermal management. The platform structure enables thermal vias or heat sinks to be positioned strategically, creating a three-dimensional thermal pathway that enhances heat removal efficiency without increasing the horizontal die area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If transistor size is increased to improve voltage breakdown, then power density decreases

Engineering Contradiction:
Improvevoltage breakdownVSAvoidpower density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The dielectric platform transfers the voltage breakdown function from the horizontal plane to the vertical dimension. By positioning the transistor active region over a raised dielectric platform, the breakdown voltage is enhanced through vertical distance rather than horizontal expansion. This allows the transistor to maintain high power density with a compact footprint while achieving the required voltage breakdown through the platform height.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8076724B2Transistor structure having an active region and a dielectric platform region
Publication Date: 2011.12.13 XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
  • US8076724B2 patent drawing
  • US8076724B2 patent drawing
  • US8076724B2 patent drawing

AI summary

A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region (1300) and a dielectric platform region (1310). A trench (80) is formed adjacent to a drain (20) of the semiconductor device to a first depth. The etch process for forming trench (80) etches the dielectric platform region (1310) to a first depth. A second trench (210) is etched in trench (80) to further isolate areas in the active region (1300). The etch process for forming the second trench (210) etches the dielectric platform region (1310) to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (80), and the second trench (210) is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.