Multi-Gate Transistor With Dielectric Sub-Fin Region
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) continue to shrink in size, there is a need for improved transistor designs that minimize current leakage between the source and drain when the gate is off, to maintain and enhance IC performance and capacity, particularly in multi-gate MOSFET transistors.
Innovation Solution
The implementation of a dielectric sub-fin region under the gate region in multi-gate metal oxide semiconductor field effect transistors (MOSFETs), which provides better isolation between the source and drain, reducing leakage current and improving channel control, using materials like amorphous silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate MOSFET transistors are used to increase IC performance and capacity, then the ability to reduce feature size is improved, but current leakage between source and drain increases
Solution Approach 1:
The fin structure is segmented into multiple gates (tri-gate or multi-gate configuration) that wrap around the channel, dividing the control into multiple zones. This segmentation allows better electrostatic control over the channel while maintaining small footprint, addressing both the productivity improvement and leakage reduction needs
Solution Approach 2:
A dielectric material is introduced as an intermediary layer within the fin structure (dielectric fin or sub-fin region) to provide electrical isolation between the source and drain regions. This intermediary dielectric layer blocks the harmful leakage current while allowing the multi-gate structure to maintain its performance benefits
2Area of stationary object
If feature size is reduced to increase IC capacity, then the number of transistors per area increases, but current leakage between source and drain worsens
Solution Approach 1:
The transistor design transitions from a planar 2D structure to a 3D multi-gate structure where gates wrap around the fin channel. This dimensional change allows the transistor to maintain effective channel control in a reduced footprint area while the vertical/3D configuration inherently provides better isolation against leakage paths
Solution Approach 2:
The dielectric material serves as an intermediary isolation layer within the fin structure, providing electrical separation between source and drain regions. This allows the transistor to achieve small footprint dimensions while the dielectric intermediary prevents direct leakage paths that would otherwise exist in scaled-down structures
3Ease of manufacture
If conventional transistor designs are used, then manufacturing simplicity is maintained, but channel control and leakage reduction are insufficient
Solution Approach 1:
The fin is segmented into multiple gate-controlled regions with a dielectric portion, creating distinct functional zones. This segmentation can be implemented using standard semiconductor fabrication processes (deposition, etching, CMP) that divide the structure into manufacturable layers, maintaining ease of manufacture while achieving superior channel control through the multi-gate geometry
Solution Approach 2:
The dielectric material is placed locally within specific regions of the fin structure (sub-fin region) where isolation is most needed, rather than throughout the entire structure. This localized application provides targeted channel control improvement and leakage reduction while minimizing impact on overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces leakage current and enhances channel control in multi-gate transistors, leading to improved performance and capacity in integrated circuits by utilizing a dielectric sub-fin region under the gate, compared to transistors without such a region.
Implementation Method 1
a dielectric material region formed in the sub-fin region below at least a portion of the gate electrode structure
Data Source
AI summary
Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.