Integrated Transistor Diode Structure for ESD Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing ESD protection devices for integrated circuits is challenging due to the need for high-voltage grounding during electrostatic discharge events, which can expose transistors to high voltage, leading to degradation or failure, and existing diode-based solutions often deviate from transistor architecture, preventing close integration and increasing area consumption.
Innovation Solution
The integration of a diode with a transistor using a sub-fin structure, where the diode is formed based on a PN junction between the sub-fin and the drain or source regions, allowing for efficient ESD protection without the need for separate diode devices, reducing area consumption and improving integration with transistor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate diode devices are used for ESD protection, then ESD protection function is achieved, but area consumption increases and integration with transistor architecture deteriorates
Solution Approach 1:
The patent combines the ESD protection diode with the transistor structure by integrating the diode's PN junction into the transistor's source/drain regions and sub-fin. The first diffusion region forms the diode anode, the sub-fin forms the diode cathode, and these are connected to the transistor's source/drain, allowing both transistor operation and ESD protection functions to coexist in a single integrated structure, thereby reducing area consumption while maintaining protection effectiveness
2Reliability
If separate diode devices are used for ESD protection, then ESD protection function is achieved, but integration with transistor architecture deteriorates
Solution Approach 1:
The patent merges the diode structure with the transistor architecture by using the transistor's existing diffusion regions and sub-fin to form the diode's PN junction. The first diffusion region (same dopant type as sub-fin) forms one terminal of the diode, while the second diffusion region (opposite dopant type) forms the other terminal. This integration allows the ESD protection function to be achieved without adding separate diode devices, thereby improving architectural integration while maintaining protection effectiveness
3Reliability
If high voltage is applied during ESD event, then ESD protection is activated, but transistor degradation or failure occurs
Solution Approach 1:
The patent converts the harmful high voltage effect into a beneficial protection mechanism by designing the integrated diode-transistor structure to enter breakdown mode during ESD events. The PN junction between the first diffusion region and sub-fin is configured to break down at high voltage, creating a controlled conduction path that safely diverts the ESD current away from the transistor channel, thereby protecting the transistor from damage while utilizing the high voltage condition itself as the trigger for protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects transistors from ESD events by integrating the diode directly with the transistor, reducing area consumption and enhancing ESD protection efficiency, while maintaining compatibility with existing transistor architectures.
Implementation Method 1
the diode is formed based on a PN junction between the sub-fin and the drain or source regions
Implementation Method 2
During an electrostatic discharge (ESD) event in an integrated circuit (IC), an input/output (I/O) pad may experience high voltage
Data Source
AI summary
An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.