Transistor Tensile Stress via Dislocation Engineering
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Solution Overview
Problem
Existing transistors face limitations in enhancing driving current and electron mobility due to insufficient tensile stress between the channel and source/drain regions.
Innovation Solution
A method is developed to form transistors with controlled dislocations in the source and drain regions by patterning a mask layer, amorphorizing, and annealing the semiconductor substrate, thereby increasing tensile stress on the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dislocations are formed between the channel region and the source/drain region to improve electron mobility, then the driving current increases, but the control of dislocation position and number becomes difficult
Solution Approach 1:
A mask layer is introduced as an intermediary tool to control the formation of dislocations. The mask layer is selectively removed to expose specific regions where dislocations should form, while protecting other regions. This mediator enables precise control over dislocation position and number, resolving the contradiction between improving electron mobility through dislocations and maintaining manufacturing precision.
Solution Approach 2:
The invention applies local quality by creating non-uniform dislocation distribution across the semiconductor substrate. Dislocations are intentionally formed only in specific source/drain regions adjacent to the channel, while other regions remain unaffected. This localized approach optimizes electron mobility in the channel without introducing unwanted defects elsewhere, achieving both improved reliability and controlled manufacturing.
2Power
If more dislocations are introduced in the source and drain regions to enhance tensile stress, then the driving current increases, but the device complexity increases
Solution Approach 1:
The mask layer is formed and patterned before the dislocation formation process. This preliminary action defines exactly where dislocations will form, allowing multiple dislocations to be introduced efficiently in a single process step. By preparing the mask structure in advance, the invention enables introduction of multiple dislocations without proportionally increasing process complexity, thus improving driving current while managing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively enhances electron mobility in the channel region by increasing the number of dislocations in the source and drain regions, leading to improved transistor performance.
Implementation Method 1
annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region
Implementation Method 2
the semiconductor substrate is annealed so as to re-crystallize the amorphous regions
Data Source
AI summary
The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.