Transistor Doped Region Epitaxy for Low-Temperature 3D Integration
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Solution Overview
Problem
In 3D integration processes for microelectronics, managing the thermal budget during the formation of upper transistor layers is challenging, especially when creating doped source and drain areas, which can lead to increased access resistance and complex process control.
Innovation Solution
A process involving the formation of a stack with insulating and active semiconductor layers, followed by selective engraving and epitaxial growth from the edge of the active layer to create doped areas, thereby reducing access resistance and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature thermal annealing is performed for dopant activation, then dopant activation is effective, but thermal budget is exceeded and lower layer transistors are damaged
Solution Approach 1:
The patent changes the temperature parameter from high temperature thermal annealing (>1000°C) to low temperature processing (below 400°C). Instead of using thermal energy for dopant activation, the invention uses ion implantation to directly introduce dopants into the semiconductor lattice, achieving activation without exceeding the thermal budget that would damage lower layer transistors in 3D stacked structures
Solution Approach 2:
The patent replaces the thermal field (heat-based annealing process) with an ion beam field (ion implantation process). By using accelerated ions to directly deposit dopants into the semiconductor material, the method eliminates the need for high temperature thermal fields while achieving effective dopant activation and concentration control
2Temperature
If SPER recrystallization process is used for dopant activation, then thermal budget is reduced, but access resistance increases due to undoped areas
Solution Approach 1:
The patent extracts and eliminates the problematic undoped areas that form during SPER recrystallization. By using ion implantation with precise dosage control, the method ensures complete and uniform dopant distribution throughout the active region, removing the undoped zones that would otherwise increase access resistance between the channel and source/drain regions
Solution Approach 2:
The patent changes the dopant concentration parameter by using controlled ion implantation doses. By optimizing the ion flux and implantation energy, the method achieves uniform dopant distribution that completely fills the active region without leaving undoped areas, while maintaining low temperature processing conditions
3Reliability
If amorphization is performed before dopant implantation, then dopant activation occurs during recrystallization, but process complexity increases and control becomes difficult
Solution Approach 1:
The patent merges the dopant implantation step with the activation step by using ion implantation that directly introduces activated dopants into the semiconductor lattice in a single process. This eliminates the need for separate amorphization and recrystallization steps, simplifying the overall process while maintaining effective dopant activation
Solution Approach 2:
The patent performs preliminary preparation of the semiconductor surface through gentle cleaning and activation treatments before ion implantation, creating optimal conditions for direct dopant incorporation. This preliminary action eliminates the need for subsequent complex recrystallization steps, as the dopants are directly incorporated into the crystal lattice during implantation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process effectively reduces the access resistance of transistors by eliminating non-doped zones and allowing for epitaxial growth without the need for a germ of epitaxy, while being compatible with low-temperature operations suitable for 3D integration.
Implementation Method 1
An ion bombardment at the edge of the spacer 11, adapted to partially amorphize the upper silicon layer 22 (topSi) of the SOI substrate, and to implant dopants in this amorphous part 22a
Implementation Method 2
After dopant implantation, dopant activation occurs during solid-phase recrystallization of the amorphous semiconductor layer
Implementation Method 3
Removing the basal portion of the first spacer by selective etching of the first material with respect to the second material of the second spacer and the semiconductor material
Data Source
Figure 1A~1C
Figure 2A~2H
AI summary
The invention relates to a method for forming at least one doped region (13) of a transistor (1), comprising the following steps: - Providing a stack comprising an insulating layer (21), an active layer (22), and a gate pattern (10) having a first side edge (100), - Removing a first portion (221) of the active layer (22) not surmounted by the gate pattern (10) and extending to the perpendicularity of the gate pattern (10), at the edge of a second portion (222, 15) of the active layer (22) surmounted by the gate pattern (10), so as to expose an edge (150) of said second portion (222, 15), said edge (150) extending substantially in a continuation of the side edge (100) of the gate pattern (10), - Forming a first spacer (11) having an L-shape and comprising a basal portion (11b) at contact of the insulating layer (21) and a lateral portion (11I) in contact with the lateral flank (100), - Form a second spacer (12) on the first spacer (11),- Remove the basal portion (11b) of the first spacer (11) by selective etching with respect to the second spacer (12), so as to expose the edge (150) of the second portion (222, 15), - Form by epitaxy from said exposed edge (150) the doped zone (13).