Transistor Doping via Selective Epitaxial Growth
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Solution Overview
Problem
Existing transistor manufacturing methods face challenges in achieving uniform doping profiles due to facet phenomena and non-uniform epitaxial layer thickness, leading to non-uniform electrical characteristics.
Innovation Solution
A method involving the formation of an impurity region on a substrate, followed by selective epitaxial growth and targeted impurity implantation into portions of the epitaxial layer where facet phenomena do not occur, ensuring uniform doping profiles and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used directly on the substrate, then the doping process is simple, but the doping profile becomes non-uniform due to facet phenomena and varying epitaxial layer thickness
Solution Approach 1:
The patent divides the doping process into two distinct stages: first forming an impurity region in the substrate, then forming an epitaxial layer, and finally performing selective doping on exposed portions of the epitaxial layer. This segmentation allows each step to be optimized independently, ensuring uniform doping profiles while managing process complexity through systematic breakdown of operations.
Solution Approach 2:
The patent performs preliminary actions by first forming the impurity region and epitaxial layer before the final doping step. The epitaxial layer is grown to a controlled thickness and patterned with openings beforehand, so that when doping occurs, it only affects specific regions. This preliminary structuring ensures that the final doping profile is uniform and precisely controlled.
2Reliability
If impurities are implanted into the entire epitaxial layer, then the doping coverage is complete, but the electrical characteristics become non-uniform due to facet phenomena
Solution Approach 1:
The patent applies local quality by creating openings in the epitaxial layer at specific locations where doping is desired. Instead of uniformly doping the entire epitaxial layer, the method selectively exposes only certain portions through patterned openings, allowing impurities to be implanted only in those regions. This ensures uniform electrical characteristics in the doped regions while avoiding facet phenomena in other areas.
Solution Approach 2:
The patent extracts or removes portions of the epitaxial layer by forming openings, thereby eliminating the regions where facet phenomena would cause non-uniform doping. By taking out the problematic areas and only doping the exposed portions, the method achieves uniform electrical characteristics without the harmful effects of facet-related non-uniformity.
3Manufacturing precision
If the epitaxial layer thickness varies, then the manufacturing process is simpler, but the doping profile uniformity deteriorates
Solution Approach 1:
The patent performs preliminary epitaxial growth to form a layer with controlled and uniform thickness before the doping step. By establishing a consistent epitaxial layer structure in advance, the subsequent doping process can proceed uniformly across all regions. This preliminary action ensures that variations in epitaxial thickness do not affect doping profile consistency.
Solution Approach 2:
The patent introduces a vertical dimension control by forming the epitaxial layer with precise thickness control before doping. The uniform thickness in the vertical dimension ensures that when impurities are implanted, they penetrate to a consistent depth across all doped regions, achieving uniform doping profiles regardless of horizontal variations in the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in transistors and semiconductor devices with uniform doping profiles and enhanced electrical characteristics, regardless of epitaxial layer shape or thickness, thereby improving overall performance.
Implementation Method 1
first impurities are implanted into the substrate to form an impurity region
Implementation Method 2
an epitaxial layer is formed on the impurity region
Implementation Method 3
second impurities are implanted into a portion of the epitaxial layer exposed by the opening
Implementation Method 4
some of the second impurities may be diffused into the impurity region
Data Source
AI summary
In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.