Transistor Base Region Doping With Selective Silicide Noise Control
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Solution Overview
Problem
Current transistor fabrication processes face challenges in achieving high beta Early voltage product with low 1/f noise and popcorn noise, as silicide formation on emitter and base contact areas can lead to reduced beta and increased noise.
Innovation Solution
A method involving sequential dopant implantations to form regions with specific carrier types, followed by forming a dielectric on sidewalls of the gate material and gate oxide before silicide formation, which acts as a silicide block to prevent unwanted silicide formation and maintain high beta while reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide formation is performed on emitter and base contact areas, then electrical conductivity is improved, but beta is reduced and noise increases
Solution Approach 1:
The patent applies different treatments to different regions: silicide formation is performed on base contact areas to improve conductivity, while emitter areas are protected from silicide formation to maintain high beta and reduce noise. This local differentiation resolves the contradiction by optimizing each region for its specific function.
Solution Approach 2:
The patent segments the contact areas into distinct regions with different silicide formation treatments. By separating emitter and base contact areas and applying selective silicide formation, the patent achieves both low noise (in emitter region) and good conductivity (in base contact region).
2Reliability
If dopant concentration is increased in emitter and base contact interfaces, then beta Early voltage product is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary dopant implantation to create high concentration regions at emitter and base contact interfaces before final device assembly. This preliminary action ensures optimal beta Early voltage product while simplifying subsequent fabrication steps by pre-establishing critical doping profiles.
Solution Approach 2:
The patent utilizes controlled changes in dopant concentration parameters during fabrication. By precisely adjusting implantation doses and energies to create specific concentration profiles at interfaces, the patent achieves high beta Early voltage product through parameter optimization rather than complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces 1/f noise and popcorn noise while maintaining a high beta Early voltage product by controlling silicide formation and increasing dopant concentration at the emitter and base contact interfaces.
Implementation Method 1
implanting dopants in a semiconductor to form a collector region having majority carriers of a first type
Implementation Method 2
annealing the semiconductor to form silicide in the second area of the emitter region
Data Source
AI summary
An integrated circuit includes a transistor that has an collector region, a base region laterally surrounded by the collector region, and an emitter region laterally surrounded by the base region. A silicide layer on the emitter region is laterally spaced apart from the base region by an unsilicided ring. The emitter region is laterally spaced apart from a base contact region that may be covered by a dielectric layer such as a gate oxide layer.