Transistor Drain Via Arrangement Reducing Parasitic Capacitance
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Solution Overview
Problem
High parasitic feedback capacitance between gate and drain structures in field effect transistors (FETs) leads to performance degradation, especially at higher frequencies, affecting device gain and stability.
Innovation Solution
The implementation of irregularly arranged drain pillars in the drain contact structures, excluding them from areas adjacent to the gate tap structures, which increases the physical distance between the gate and drain pillars, thereby reducing parasitic feedback capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If drain pillars are regularly spaced and extend continuously along the drain region, then electrical connectivity is maximized, but parasitic feedback capacitance between gate and drain structures increases
Solution Approach 1:
The patent extracts or removes drain pillars from specific areas adjacent to the gate structure, creating a gap or separation zone. This selectively removes the harmful capacitive coupling while maintaining electrical connectivity through the remaining drain pillars in other regions.
Solution Approach 2:
The patent applies different configurations of drain pillars in different regions: continuous drain pillars in regions away from the gate for maximum connectivity, and excluded or reduced drain pillars in regions adjacent to the gate to minimize parasitic capacitance. This local differentiation resolves the contradiction.
2Area of stationary object
If drain pillars are positioned close to the gate structure, then area utilization is maximized, but electromagnetic coupling and parasitic capacitance increase
Solution Approach 1:
The patent extracts drain pillars from the immediate vicinity of the gate structure, creating a clearance zone that reduces electromagnetic coupling while maintaining reasonable area utilization through optimized placement of remaining drain pillars.
Solution Approach 2:
The patent introduces asymmetric spacing between drain pillars and the gate structure, with larger spacing in regions where electromagnetic coupling is most problematic. This asymmetric arrangement reduces parasitic effects while maintaining compact overall design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in reduced parasitic feedback capacitance, leading to improved device gain and stability, and other beneficial effects on FET performance.
Implementation Method 1
electromagnetic coupling between the gate and drain structures, and more particularly to parasitic feedback capacitance between the gate and drain structures, referred to as Cgd
Data Source
AI summary
An embodiment of a transistor die includes a semiconductor substrate a drain region, a channel region, a drain terminal, and a conductive gate tap. The conductive gate tap includes a distal end that is coupled to a gate structure over the channel region. A first segment of the drain region is adjacent to the distal end of the gate tap. The drain terminal includes a drain runner formed from one or more portions of the patterned conductive layers. A plurality of drain pillars electrically connects the drain runner to second and third segments of the drain region, and a plurality of second drain pillars electrically connect the drain runner and the third drain region segment. The build-up structure over the second drain region segment between the first and second drain pillars is devoid of electrical connections between the drain runner and the drain region.