Transistor with Extended Drain Region for High Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistor devices face challenges in achieving high breakdown voltage and area efficiency, particularly in power and high-voltage applications, where extended drain regions are crucial but often require complex masking steps and are not easily scalable.
Innovation Solution
The transistor device features a vertical channel region within a trench with a horizontally oriented extended drain region, allowing for adjustable breakdown voltage and eliminating the need for a photolithographic mask in forming the field plate structure, which is achieved through a conductive sidewall spacer structure along the sidewall of the control terminal material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional extended drain regions are used to achieve high breakdown voltage, then breakdown voltage is improved, but device area increases and manufacturing complexity increases due to complex masking steps
Solution Approach 1:
The extended drain region is configured to extend vertically from the drain contact towards the gate, utilizing the vertical dimension rather than horizontal expansion. This allows the drift region to achieve the necessary length for high breakdown voltage while maintaining a compact horizontal footprint, thus improving breakdown voltage without increasing device area.
Solution Approach 2:
The patent extracts the extended drain region formation from the conventional planar process by using a separate vertical implantation step. The drift region is formed by implanting dopants vertically through the gate structure into the drain region, eliminating the need for complex lateral masking steps and reducing manufacturing complexity while achieving the desired extended drain configuration.
2Strength
If conventional extended drain regions are used to achieve high breakdown voltage, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The patent extracts the extended drain region formation from the conventional planar process by using a separate vertical implantation step. The drift region is formed by implanting dopants vertically through the gate structure into the drain region, eliminating the need for complex lateral masking steps and reducing manufacturing complexity while achieving the desired extended drain configuration.
Solution Approach 2:
The gate structure serves a dual function: as the control electrode for the transistor and as a mask for the vertical implantation step that forms the drift region. This self-service approach eliminates the need for separate complex masking steps, reducing manufacturing complexity while enabling precise formation of the extended drain region.
3Area of stationary object
If vertical channel region is used to reduce device area, then area efficiency is improved, but scalability of extended drain region length is reduced
Solution Approach 1:
The patent enables dynamic adjustment of the extended drain region length by varying the implantation depth parameters. The vertical implantation process allows independent control of drift region length through energy and dosage adjustments, providing scalability while maintaining the compact vertical channel structure. This dynamic parameter control enables adaptation to different voltage requirements without changing the overall device geometry.
Data Source
AI summary
A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.