Transistor Edge Channel Formation Prevention via Guard Ring
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Solution Overview
Problem
High-voltage transistors in display driver integrated circuits (DDIs) experience a 'hump phenomenon' due to lower well-doping concentration at the boundary surface between the active region and isolation region, leading to two threshold voltages and increased sub-threshold leakage current.
Innovation Solution
A transistor design with a substrate having a device active region defined by an isolation layer, including a channel active region with edges contacting the isolation layer, where the gate electrode does not overlap the edges, and a drain field dielectric thicker than the gate dielectric is used to prevent channel formation in the edges, reducing dopant segregation effects and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the well-doping concentration is lowered to increase junction breakdown voltage, then the breakdown voltage increases, but dopant segregation occurs at the boundary surface between active region and isolation region, causing channel formation at lower voltages and the hump phenomenon
Solution Approach 1:
The patent applies local quality by creating a guard ring structure with different doping characteristics around the periphery of the active region. The guard ring has a doping concentration and type that differs from both the well region and the isolation region, locally compensating for dopant segregation effects at the boundary surface. This localized structural modification prevents channel formation at the edges while maintaining the overall low well-doping concentration needed for high breakdown voltage.
Solution Approach 2:
The guard ring acts as an intermediary structure between the well region and the isolation region. It mediates the dopant segregation issue by providing a transition zone that prevents direct contact between the low-doping well and the isolation region, thereby eliminating the hump phenomenon caused by edge channel formation while preserving the high-voltage characteristics.
2Ease of operation
If the gate electrode overlaps the channel active region edges, then better gate control is achieved, but channels form in the edges at lower voltages due to dopant segregation, increasing sub-threshold leakage current
Solution Approach 1:
The patent modifies the local structure at the channel edges by introducing the guard ring, which changes the electrical characteristics of the edge regions. This local modification allows the gate electrode to overlap the channel active region for better control while the guard ring prevents harmful channel formation at the edges by compensating for dopant segregation, thereby reducing sub-threshold leakage current.
Solution Approach 2:
The patent segments the channel active region by introducing the guard ring structure that separates the edge regions from the central channel region. This segmentation allows independent optimization: the gate electrode can overlap the central region for control, while the guard ring protects the edge segments from forming leakage channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents the 'hump phenomenon' and reduces sub-threshold leakage current, enhancing the reliability and operation of high-voltage transistors at increased voltages by maintaining a stable breakdown voltage and minimizing electric charge trapping in the isolation layer.
Implementation Method 1
The well-doping concentration on a boundary surface between an active region and an isolation region may be lowered due to dopant segregation
Data Source
AI summary
A transistor, a display driver integrated circuit having the transistor, and a method for fabricating a transistor are provided. A transistor, according to example embodiments, may include a substrate with a device active region defined by an isolation layer, wherein the device active region may include a source active region, a channel active region, and a drain active region and the channel active region may include a pair of edges contacting the isolation layer. The transistor, according to example embodiments, may also include a gate electrode overlapping the channel active region, wherein the edges are exposed beyond a periphery of the gate electrode, a gate dielectric between the gate electrode and the channel active region, and source and drain impurity regions within the source and drain active regions.