Transistor Edge Region Doping for CMOS Image Sensor Noise Reduction
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Solution Overview
Problem
CMOS image sensors face high random telegraph signal (RTS) noise in pixel source follower transistors, which decreases image sensor sensitivity, and enlarging source follower transistors to reduce noise is not feasible in all designs.
Innovation Solution
The implementation of novel transistor designs with a higher voltage threshold proximate shallow trench isolation (STI) regions, achieved through techniques such as implanting dopants in STI regions or increasing gate dielectric thickness at edge regions, to direct current flow away from noise-prone edge regions and enhance central region current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If source follower transistors are enlarged to reduce RTS noise, then noise is reduced, but device area increases and integration density decreases
Solution Approach 1:
The patent applies local quality by creating non-uniform dopant concentration distribution within the channel region. Specifically, higher dopant concentration is introduced at the edge regions near STI structures while maintaining lower concentration in the central channel region. This local differentiation allows the transistor to operate with reduced RTS noise from edge regions while preserving compact dimensions, resolving the contradiction between noise reduction and area minimization.
Solution Approach 2:
The patent changes the dopant concentration parameter spatially within the transistor structure. By adjusting the dopant concentration at different locations (higher at edges, lower at center) through selective implantation processes, the electrical characteristics are optimized to reduce RTS noise without requiring increased device area, thus resolving the technical contradiction.
2Object-affected harmful factors
If dopant concentration is increased at edge regions, then RTS noise is reduced, but manufacturing complexity increases
Solution Approach 1:
The doping process is segmented into multiple sequential steps with different dopant types and concentrations. First, a baseline dopant concentration is established throughout the channel, then additional dopant is selectively implanted at edge regions in subsequent steps. This segmentation allows precise spatial control of dopant distribution while using standard semiconductor manufacturing techniques, managing manufacturing complexity while achieving noise reduction.
Solution Approach 2:
The patent performs preliminary doping actions to establish the base channel characteristics before final edge-region doping adjustments. By pre-establishing the overall dopant profile and then making targeted modifications at edge regions, the manufacturing process becomes more manageable while achieving the desired non-uniform concentration distribution for noise reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces RTS noise without requiring larger transistor sizes, improving image sensor sensitivity by ensuring more current flows through the central region of the channel, thereby minimizing noise at edge regions.
Implementation Method 1
implanting dopants in STI regions
Implementation Method 2
enhance central region current flow
Data Source
AI summary
Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.