Transistor Cell Electrode Layout With Selective Airgaps for RF Behavior
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Solution Overview
Problem
In transistor devices with parallelly coupled transistor cells, parasitic capacitances between electrodes negatively impact radio frequency behavior, and while airgaps can reduce these capacitances, they increase the device's area requirement on a chip die or wafer.
Innovation Solution
The transistor device incorporates a plurality of transistor cells with load electrodes arranged in a specific pattern, where a first pitch between certain pairs of load electrodes is smaller than a second pitch, and airgaps are provided only between the load electrodes of the second subset of pairs, thereby optimizing the reduction of parasitic capacitances without significantly increasing the device's area requirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If airgaps are provided between adjacent load electrodes to reduce parasitic capacitances, then radio frequency behavior is improved, but the pitch between electrodes increases and the device area increases
Solution Approach 1:
The patent applies local quality by providing airgaps selectively between specific pairs of adjacent load electrodes (second subset) rather than uniformly between all adjacent electrodes. This creates different local structures: some regions have airgaps for capacitance reduction, while other regions maintain smaller pitch for area efficiency. The differentiated local configuration optimizes the trade-off between radio frequency performance and device area.
2Object-generated harmful factors
If airgaps are provided between all adjacent load electrodes, then parasitic capacitances are reduced, but the pitch between electrodes increases significantly
Solution Approach 1:
The patent extracts the airgap feature from a universal application and applies it selectively only to specific pairs of adjacent load electrodes (second subset). By removing the airgap structure from regions where it is not needed, the overall pitch between electrodes is reduced while still achieving parasitic capacitance reduction in the critical regions where airgaps are provided.
3Area of stationary object
If the pitch between all adjacent load electrodes is reduced to minimize device area, then area requirement is reduced, but parasitic capacitances increase and radio frequency behavior deteriorates
Solution Approach 1:
The patent implements local quality by creating two distinct pitch regions: a first subset of adjacent load electrode pairs with smaller pitch for area efficiency, and a second subset with larger pitch (airgaps) for radio frequency performance. This localized differentiation allows the device to achieve compact overall area while maintaining excellent RF characteristics in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitances, particularly drain-source capacitances, while minimizing the increase in area requirement, thereby enhancing the radio frequency performance of the transistor device.
Implementation Method 1
parasitic capacitances between the corresponding electrodes (for example drain-source capacitances, gate-drain capacitances, gate-source capacitances, source-body capacitances and drain-body capacitances) inevitably exist
Data Source
AI summary
A transistor device includes a plurality of transistor cells. Each transistor cell includes two load electrodes and a control electrode. The two load electrodes of the transistor cells are arranged spaced apart from each other in a first direction. A first pitch between adjacent load electrodes of a first subset of pairs of the two load electrodes is smaller than a second pitch between adjacent load electrodes of a second subset of pairs of the two load electrodes. Airgaps are provided between adjacent load electrodes of the second subset of pairs.