Transistor Fabrication Using Etch Stop Layer Dummy Pattern

Solution Overview

Problem

The shortening of transistor channel length in semiconductor devices due to decreased design rules leads to short channel effects, causing increased leakage current, reduced refresh properties, and non-uniform threshold voltage distribution, which hinders operational stability and uniformity across memory cell transistors.

Innovation Solution

A method is developed to fabricate transistors with uniform channel lengths by forming an etch stop layer pattern, etching a recess trench, and filling it with a gate, ensuring consistent channel width and threshold voltage distribution through precise etching and insulation layer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the channel length is shortened to increase integration density, then the device area is reduced, but the short channel effect increases causing non-uniform threshold voltage and operational instability

Engineering Contradiction:

Improvedevice areaVSAvoidchannel length uniformity

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a dummy pattern (isolation pattern) before the gate electrode formation. This dummy pattern is specifically designed to compensate for etching non-uniformity that would otherwise occur during the recess groove formation. By pre-positioning this compensatory structure, the invention ensures that the actual channel length becomes uniform across all transistors, thereby resolving the contradiction between reduced device area and maintained channel length uniformity.

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If selective etching is used to form recess grooves, then the gate can be formed to fill the recess, but the etch depth varies from position to position causing non-uniform channel length

Engineering Contradiction:

Improverecess groove formationVSAvoidrecess groove depth uniformity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a dummy pattern (isolation pattern) as an intermediary element during the etching process. This dummy pattern acts as a mediator that compensates for the non-uniform etch depth inherent in selective etching. By placing this intermediary structure, the invention ensures that the recess groove depth becomes uniform across different positions, thereby maintaining consistent channel length while still allowing the recess groove formation process to proceed easily.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If the design rule is decreased to increase integration, then more transistors fit in the area, but the threshold voltage control margin is sharply weakened

Engineering Contradiction:

Improveintegration densityVSAvoidthreshold voltage control

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a dummy pattern (isolation pattern) before the gate electrode formation. This dummy pattern is specifically designed to compensate for etching non-uniformity that would otherwise occur during the recess groove formation. By pre-positioning this compensatory structure, the invention ensures that the actual channel length becomes uniform across all transistors, thereby resolving the contradiction between reduced device area and maintained channel length uniformity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7851298B2Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation

Publication Date: 2010.12.14 MIMIRIP LLC

AI summary

Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.