Transistor Etching Stop Layer for Polysilicon Thickness Uniformity
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Solution Overview
Problem
Conventional top gate transistors suffer from damage to the polycrystalline silicon layer during the etching process, leading to non-uniform thickness, decreased electron mobility, increased current leakage, and reduced reliability due to the etching of the active layer.
Innovation Solution
A transistor design incorporating an etching stop structure with distinct portions and ohmic contact regions that extend over the crystalline semiconductor layer, allowing for precise control during etching and minimizing damage to the active layer, along with a manufacturing method that forms a patterned etching stop structure and ohmic contact layers using identical masks for uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ohmic contact layer is etched to form source and drain regions, then the electrical connection is improved, but the polycrystalline silicon active layer is damaged and thickness uniformity deteriorates
Solution Approach 1:
A silicon oxide layer is introduced as an intermediary protective layer between the etching process and the polycrystalline silicon active layer. This layer serves as an etching stop layer that prevents direct contact between the etchant and the active layer, thereby protecting the active layer from damage while still allowing the etching process to proceed for forming source and drain regions.
Solution Approach 2:
The silicon oxide protective layer is formed in advance before the etching process. This preliminary action ensures that the active layer is protected before any etching occurs, preventing thickness non-uniformity and damage during the subsequent etching of the ohmic contact layer to form source and drain regions.
2Ease of manufacture
If the polycrystalline silicon layer is etched during ohmic contact layer processing, then the source and drain regions are formed, but electron mobility decreases and current leakage increases
Solution Approach 1:
The silicon oxide layer acts as a protective intermediary that allows the etching process to proceed for source and drain formation while preventing the etchant from reaching and damaging the polycrystalline silicon active layer, thereby maintaining electron mobility and preventing current leakage.
Solution Approach 2:
The silicon oxide protective layer is deposited beforehand to cushion and absorb the harmful effects of the etching process. This layer sacrifices itself to protect the active layer from etching damage, ensuring that electron mobility is maintained and current leakage is prevented while still allowing source and drain regions to be formed.
3Device complexity
If conventional etching process is used without protective layer, then the manufacturing process is simple, but the active layer thickness becomes non-uniform and electrical properties deteriorate
Solution Approach 1:
A silicon oxide protective layer is introduced as an intermediary layer that prevents direct etching of the active layer. This simple addition of a protective layer significantly improves active layer thickness uniformity and electrical properties without substantially complicating the manufacturing process.
Solution Approach 2:
The silicon oxide protective layer is formed in advance using a simple deposition process before the etching step. This preliminary protective action ensures uniform active layer thickness and good electrical properties while adding minimal complexity to the overall manufacturing process.
Data Source
AI summary
This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.