Transistor-Level Fault Simulation Defect Injection
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Solution Overview
Problem
Current fault simulation methods for integrated circuits are inefficient, particularly in analog and mixed-signal circuits, as they often require extensive simulation times and may not accurately inject defects that are more likely to occur due to manufacturing processes, such as shorts and opens between adjacent nodes, which are difficult to predict without layout information.
Innovation Solution
The method involves selecting circuit elements for defect injection based on their type and netlist level, with different defects injected for design-intent and parasitic elements, allowing for faster simulation by using layout information when available and design-intent netlists when layout information is not, thereby focusing on more likely defects without simulating all possible variations in parasitic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fault simulation is performed by injecting all possible defects into transistor-level netlists, then measurement precision and reliability of fault detection are improved, but simulation time increases significantly
Solution Approach 1:
The patent segments the fault simulation process into distinct phases: defect injection phase using high-level netlists for speed, and verification phase using transistor-level netlists for accuracy. This segmentation allows the system to benefit from both fast high-level simulation and accurate low-level simulation without combining their drawbacks
Solution Approach 2:
The patent applies partial action by injecting only the most critical and likely defects into transistor-level netlists rather than all possible defects. High-level netlists are used to identify and prioritize defects that are most likely to occur or have the greatest impact, reducing the number of transistor-level simulations needed
2Manufacturing precision
If layout information is used to guide defect injection, then manufacturing precision of defect modeling is improved, but device complexity increases due to requiring multiple netlist levels
Solution Approach 1:
The patent implements a dynamic netlist selection mechanism that automatically chooses between high-level and low-level netlists based on the simulation stage and available layout information. The system adapts its complexity level rather than being statically tied to one netlist type, optimizing both accuracy and manageability
Solution Approach 2:
The patent introduces an intermediary defect injection engine that translates layout information into targeted defect injections on appropriate netlist levels. This intermediary layer manages the complexity of coordinating multiple netlist levels by providing a unified interface for defect injection across different abstraction levels
3Reliability
If all circuit elements are selected for defect injection, then fault coverage is improved, but simulation time increases due to processing more elements
Solution Approach 1:
The patent applies local quality by differentiating defect injection strategies for different circuit elements and netlist levels. Critical elements identified through high-level simulation receive detailed transistor-level defect injection, while less critical elements are handled at the higher level, optimizing resource allocation across the circuit
Data Source
AI summary
Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.