Transistor Field Plate Capacitance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for producing transistor components struggle to precisely control the gate-drain capacitance, which affects the switching speed and behavior of the transistor, as it is dependent on the overlap area between the gate electrode and the drain zone, making it challenging to reproduce or set this parameter accurately during production.
Innovation Solution
A method involving the production of a transistor component with a field plate, where a semiconductor body is processed to have trenches, a field plate dielectric layer is applied, and a field plate layer is formed within the trenches, followed by partial removal of the dielectric layer to achieve precise control over the field plate dimensions and overlap area, thereby influencing the gate-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional production methods are used to form the gate electrode and drain zone, then the manufacturing process is simple, but the overlap area between gate electrode and drain zone cannot be precisely controlled, resulting in poor gate-drain capacitance reproduction
Solution Approach 1:
The field plate dielectric layer is applied in advance before forming the gate electrode, and the field plate structure is preliminarily formed with controlled dimensions. This preliminary action establishes a reference structure that enables precise control of the subsequent gate electrode overlap area with the drain zone, solving the precision problem while maintaining process feasibility
Solution Approach 2:
The field plate dielectric layer serves as an intermediary element between the drain zone and the gate electrode. By controlling the thickness and lateral dimensions of this dielectric layer, the patent indirectly controls the overlap area between gate and drain, achieving precise capacitance control without requiring direct precision control of the gate-drain interface
2Speed
If the gate-drain capacitance is not precisely controlled, then the production process is faster, but the switching speed and switching behavior of the transistor cannot be optimized
Solution Approach 1:
The patent controls the gate-drain capacitance by precisely adjusting physical parameters of the field plate structure, specifically the thickness and lateral dimensions of the field plate dielectric layer. By changing these parameters during production, the overlap area is controlled, which directly determines the gate-drain capacitance value and enables optimization of switching speed
3Manufacturing precision
If the overlap area is precisely controlled through conventional methods, then the gate-drain capacitance can be set accurately, but the production complexity increases significantly
Solution Approach 1:
The field plate dielectric layer structure serves as a self-aligning reference for subsequent processing steps. The controlled lateral dimensions of this dielectric layer automatically define the overlap region, enabling the structure to self-determine the capacitance characteristics without requiring complex external alignment or measurement processes, thus maintaining ease of manufacture while achieving high precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise reproduction of the gate-drain capacitance, enhancing the switching speed and behavior of the transistor component by accurately controlling the overlap area between the gate electrode and the drain zone, leading to improved switching performance.
Implementation Method 1
uncovering the first side of the semiconductor body by using a polishing method; partially removing the field plate dielectric layer from the at least one first trench proceeding from the first side
Data Source
AI summary
A method for producing a transistor component having a field plate. One embodiment includes providing a semiconductor body having a first side, and including a first trench extending into the semiconductor body. A field plate dielectric layer is produced on the first side and at uncovered areas of the first trench such that a residual trench remains. A field plate layer is produced in the residual trench. The first side of the semiconductor body is uncovered using a polishing method. The field plate dielectric layer is partially removed from the at least one first trench proceeding from the first side.