High-Voltage Transistor Field Plate for Wafer-Level Dielectric Testing
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Solution Overview
Problem
Existing high voltage transistors face challenges in effectively testing dielectric layers during wafer probe testing, leading to costly packaging of both good and bad dies, as defects in dielectric layers are not detectable until after packaging is complete.
Innovation Solution
The implementation of separate probe pads for the source and source field plates in high voltage transistors allows for individual control of voltages, enabling overvoltage stress testing at the wafer probe stage to identify and scrap defective devices, thereby reducing packaging waste and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate probe pads for source and source field plate are implemented, then testing capability and defect detection are improved, but device complexity increases
Solution Approach 1:
The source terminal is segmented into two separate electrically independent terminals: source contact probe pad and source field plate probe pad. This segmentation allows independent voltage control and separate testing of each terminal, enabling detection of dielectric defects that would otherwise be undetectable. The physical separation into distinct probe pads facilitates independent probing during wafer-level testing.
Solution Approach 2:
A separate probe pad structure acts as an intermediary between the testing equipment and the transistor terminals. By introducing dedicated probe pads for source contact and source field plate, the testing system can independently control and measure voltages at each terminal, enabling comprehensive defect detection without modifying the transistor structure itself.
2Measurement precision
If overvoltage stress testing is performed at wafer probe testing, then defect identification is improved, but testing time and process complexity increase
Solution Approach 1:
Overvoltage stress testing is performed at the wafer probe testing stage, before packaging. This preliminary action identifies defective devices early in the manufacturing process, preventing defective units from entering the packaging process. The separate probe pads enable this early stress testing by providing independent access to source and source field plate terminals.
Solution Approach 2:
The patent converts the potential harm of extended testing time into a benefit by performing comprehensive stress testing at the wafer level. Although testing takes longer, it prevents the greater waste of packaging defective devices. The separate probe pads enable thorough testing that identifies defects early, turning the extended testing time into a cost-saving measure by preventing downstream rework and scrap.
3Manufacturing precision
If separate voltage control on source and source field plate is enabled, then dielectric layer defect detection is improved, but device structure complexity increases
Solution Approach 1:
The voltage control system is segmented into independent control channels for source contact and source field plate. Each terminal has its own probe pad and voltage control circuitry, enabling separate voltage application and measurement. This segmentation allows independent stress testing of dielectric layers between different terminal pairs, improving defect detection capability.
Solution Approach 2:
The patent utilizes parameter changes by applying different voltage levels and stress conditions to source contact and source field plate independently. By varying voltage parameters separately at each terminal, the system can detect dielectric defects through leakage current measurements and breakdown voltage testing, achieving high manufacturing precision without requiring complex multi-terminal structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables early detection of dielectric defects at the wafer probe stage, avoiding the need for costly burn-in tests and reducing material and time expenses by identifying and scrapping defective devices before packaging.
Implementation Method 1
the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain
Data Source
AI summary
In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.