Transistor Gate and Contact Sizing for Leakage and Resistance
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Solution Overview
Problem
Conventional semiconductor fabrication methods do not adequately optimize transistors for specific applications, leading to issues like leakage current and parasitic resistance in memory and logic devices, respectively, due to uniform sizing approaches that fail to address unique performance concerns.
Innovation Solution
The solution involves configuring gate structures and source/drain contacts differently based on the type of IC application, with enlarged gate structures for memory devices to reduce leakage current and enlarged source/drain contacts for logic devices to minimize parasitic resistance, optimizing performance for each application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform transistor sizing is used across all devices, then manufacturing simplicity is maintained, but leakage current increases in memory devices and parasitic resistance increases in logic devices
Solution Approach 1:
The patent applies different sizing rules to different transistor types based on their specific application requirements. Memory device transistors are sized with wider channels to minimize leakage current, while logic device transistors are sized with larger source/drain contacts to minimize parasitic resistance. This local differentiation resolves the contradiction by optimizing each transistor type for its specific function rather than using a uniform approach.
2Productivity
If transistor dimensions are scaled down uniformly, then production efficiency increases and costs decrease, but leakage current and parasitic resistance increase
Solution Approach 1:
The patent changes the dimensional parameters of transistors based on their application type. Memory device transistors maintain larger channel widths to reduce leakage, while logic device transistors have larger contact dimensions to reduce parasitic resistance. This selective parameter adjustment allows scaling benefits while maintaining performance requirements for different device types.
3Reliability
If gate and source/drain contact sizes are optimized for specific applications, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the transistor population into different categories (memory devices vs. logic devices) and applies different sizing rules to each segment. This segmentation allows performance optimization for each type while managing fabrication complexity through systematic classification and application of different design rules to different segments of the circuit.
Data Source
AI summary
A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.