Adjacent Transistor Gate Structure for Void-Free Dielectric Fill
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, manufacturing defects and voids in dielectric materials between adjacent transistors become more prevalent, affecting device performance and integration density.
Innovation Solution
A dielectric material is used to separate metal gates of adjacent transistors, with the upper portion of the opening widened to improve gap fill window and reduce voids, while maintaining effective gate width through controlled etching processes like atomic layer etch (ALE).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but manufacturing defects and voids in dielectric materials become more prevalent
Solution Approach 1:
The opening structure is segmented into different regions with different widths - a first opening region with a first width and a second opening region with a second width that is greater than the first width. This segmentation allows the dielectric material to be deposited more effectively without voids while maintaining the required gate width, thus resolving the contradiction between integration density and manufacturing precision
Solution Approach 2:
Different regions of the opening are given different local qualities - the upper portion (second opening region) has a larger width to facilitate complete dielectric material filling, while the lower portion (first opening region) maintains a smaller width to preserve effective gate width. This local differentiation enables both high integration density and low defect rates
2Manufacturing precision
If the opening width is increased to improve dielectric material filling, then voids are reduced, but the effective gate width may be compromised
Solution Approach 1:
The opening is divided into two segmented regions with different width characteristics. The first opening region has a smaller width to maintain effective gate width, while the second opening region has a larger width to ensure complete dielectric material filling without voids. This segmentation resolves the contradiction between filling quality and gate width
Solution Approach 2:
The opening structure transitions from a uniform two-dimensional cross-section to a three-dimensional structure with varying width along the vertical dimension. The upper portion is widened in the lateral dimension while the lower portion maintains its original width, enabling both improved material filling and preserved gate width through dimensional variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing defects and enhances device performance by ensuring complete filling of dielectric material, thereby maintaining the integrity of the gate structure and improving integration density.
Implementation Method 1
the etching process is an atomic layer etch process
Data Source
AI summary
A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.